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This commit is contained in:
Benjamin
parent
26c28a829d
commit
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115
CPUProject.bdf
115
CPUProject.bdf
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@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Copyright (C) 2019 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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||||
(including device programming or simulation files), and any
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||||
associated documentation or information are expressly subject
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||||
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@ -16,6 +16,115 @@ the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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(header "graphic" (version "1.4"))
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(rect 608 256 784 272)
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(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
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(rect 504 240 568 288)
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(text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6)))
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(text "inst" (rect 3 37 20 49)(font "Arial" ))
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(port
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(pt 0 16)
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(input)
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(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
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(text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible))
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@ -41,7 +41,7 @@ set_global_assignment -name DEVICE AUTO
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set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
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set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
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set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name BDF_FILE CPUProject.bdf
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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@ -50,3 +50,4 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
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BIN
CPUProject.qws
BIN
CPUProject.qws
Binary file not shown.
178
Waveform.vwf
Normal file
178
Waveform.vwf
Normal file
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@ -0,0 +1,178 @@
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/*<simulation_settings>
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<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off CPUProject -c CPUProject --vector_source="C:/Users/Benjamin/Desktop/CPUProject/Waveform.vwf" --testbench_file="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off CPUProject -c CPUProject --vector_source="C:/Users/Benjamin/Desktop/CPUProject/Waveform.vwf" --testbench_file="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/" CPUProject -c CPUProject</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/" CPUProject -c CPUProject</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vlog -work work CPUProject.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.CPUProject_vlg_vec_tst
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vcd file -direction CPUProject.msim.vcd
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vcd add -internal CPUProject_vlg_vec_tst/*
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vcd add -internal CPUProject_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vlog -work work CPUProject.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.CPUProject_vlg_vec_tst
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vcd file -direction CPUProject.msim.vcd
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vcd add -internal CPUProject_vlg_vec_tst/*
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vcd add -internal CPUProject_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
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/*
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||||
WARNING: Do NOT edit the input and output ports in this file in a text
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||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
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||||
/*
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||||
Copyright (C) 2019 Intel Corporation. All rights reserved.
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||||
Your use of Intel Corporation's design tools, logic functions
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||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
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||||
*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("X")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("Y")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("Z")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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TRANSITION_LIST("X")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 50;
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LEVEL 0 FOR 10.0;
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LEVEL 1 FOR 10.0;
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}
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}
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}
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TRANSITION_LIST("Y")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 25;
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LEVEL 0 FOR 20.0;
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LEVEL 1 FOR 20.0;
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}
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}
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}
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TRANSITION_LIST("Z")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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DISPLAY_LINE
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{
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CHANNEL = "X";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 0;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "Y";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 1;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "Z";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 2;
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TREE_LEVEL = 0;
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}
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TIME_BAR
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{
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TIME = 0;
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MASTER = TRUE;
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}
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;
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