From 14418c87259d26229a3b20400aa6d434e5c1f1f6 Mon Sep 17 00:00:00 2001 From: Benjamin Date: Wed, 20 May 2020 19:24:20 +0100 Subject: [PATCH] VCS Test --- CPUProject.bdf | 115 +++++++++++++++++++++++++++++++- CPUProject.qsf | 5 +- CPUProject.qws | Bin 673 -> 1244 bytes Waveform.vwf | 178 +++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 293 insertions(+), 5 deletions(-) create mode 100644 Waveform.vwf diff --git a/CPUProject.bdf b/CPUProject.bdf index 0349cfa..abb829a 100644 --- a/CPUProject.bdf +++ b/CPUProject.bdf @@ -4,9 +4,9 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 2018 Intel Corporation. All rights reserved. +Copyright (C) 2019 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic +and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject @@ -16,6 +16,115 @@ the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details. +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. */ (header "graphic" (version "1.4")) +(pin + (input) + (rect 296 224 464 240) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "X" (rect 5 0 11 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 296 288 464 304) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "Y" (rect 5 0 13 17)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 608 256 784 272) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "Z" (rect 90 0 97 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(symbol + (rect 504 240 568 288) + (text "AND2" (rect 1 0 25 10)(font "Arial" (font_size 6))) + (text "inst" (rect 3 37 20 49)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) + (text "IN1" (rect 2 7 19 19)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 0 32) + (input) + (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) + (text "IN2" (rect 2 23 19 35)(font "Courier New" (bold))(invisible)) + (line (pt 0 32)(pt 14 32)) + ) + (port + (pt 64 24) + (output) + (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible)) + (line (pt 42 24)(pt 64 24)) + ) + (drawing + (line (pt 14 12)(pt 30 12)) + (line (pt 14 37)(pt 31 37)) + (line (pt 14 12)(pt 14 37)) + (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) + ) +) +(connector + (pt 496 256) + (pt 496 232) +) +(connector + (pt 504 256) + (pt 496 256) +) +(connector + (pt 496 232) + (pt 464 232) +) +(connector + (pt 464 296) + (pt 496 296) +) +(connector + (pt 496 296) + (pt 496 272) +) +(connector + (pt 496 272) + (pt 504 272) +) +(connector + (pt 568 264) + (pt 608 264) +) diff --git a/CPUProject.qsf b/CPUProject.qsf index daf810d..92c9c98 100644 --- a/CPUProject.qsf +++ b/CPUProject.qsf @@ -41,7 +41,7 @@ set_global_assignment -name DEVICE AUTO set_global_assignment -name TOP_LEVEL_ENTITY CPUProject set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020" -set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name BDF_FILE CPUProject.bdf set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top @@ -49,4 +49,5 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf \ No newline at end of file diff --git a/CPUProject.qws b/CPUProject.qws index b591087d55c24927deb64f7257c4d6f7db26bc97..1f431634be6d68c24a932bfa5d2177bbdb5f804b 100644 GIT binary patch delta 302 zcmZ8b%?bfw6g_i8$t%p#LP;?wWx)d|7E+{;L6e0cWg%JF(>#H)m&fo7lvglozvuhN z!oA&l&bjwH-ESK_hu398HkDOKCV;U!oC=0W-ZRBn%94`{e(|SEn8QXE8J0pDeI$^k zw$LL>F>O`?9VC&{EJ;gF`joC#GM&_%yYlZv<+9_?y!)qLxuq>2tlJSYBKjX0Xofl?xp-JXI+n FcmskLJnjGh delta 62 zcmcb^xsY{&KO^JBfL1nkTLuPZ+sO&cCnqmqEMsEcJXwY*Q-<9JD4NCq1^@s5{|CZA IE+Z2I03!qvT>t<8 diff --git a/Waveform.vwf b/Waveform.vwf new file mode 100644 index 0000000..393a543 --- /dev/null +++ b/Waveform.vwf @@ -0,0 +1,178 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off CPUProject -c CPUProject --vector_source="C:/Users/Benjamin/Desktop/CPUProject/Waveform.vwf" --testbench_file="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off CPUProject -c CPUProject --vector_source="C:/Users/Benjamin/Desktop/CPUProject/Waveform.vwf" --testbench_file="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/" CPUProject -c CPUProject +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Users/Benjamin/Desktop/CPUProject/simulation/qsim/" CPUProject -c CPUProject +onerror {exit -code 1} +vlib work +vlog -work work CPUProject.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.CPUProject_vlg_vec_tst +vcd file -direction CPUProject.msim.vcd +vcd add -internal CPUProject_vlg_vec_tst/* +vcd add -internal CPUProject_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work CPUProject.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.CPUProject_vlg_vec_tst +vcd file -direction CPUProject.msim.vcd +vcd add -internal CPUProject_vlg_vec_tst/* +vcd add -internal CPUProject_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("X") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Y") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Z") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("X") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("Y") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 25; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + } + } +} + +TRANSITION_LIST("Z") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "X"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Z"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +;