ELEC40006-P1-CW/instr.mif

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-- Copyright (C) 2019 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
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-- Quartus Prime generated Memory Initialization File (.mif)
WIDTH=16;
DEPTH=2048;
ADDRESS_RADIX=UNS;
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DATA_RADIX=HEX;
CONTENT BEGIN
0 : 8800;
1 : 9001;
2 : 26D0;
3 : 291A;
4 : 2D20;
5 : 3161;
6 : 3448;
7 : 3993;
8 : 3AA5;
9 : D002;
10 : 3CE2;
11 : A003;
12 : 9804;
13 : 38A5;
14 : 3FC0;
15 : 419D;
16 : 304F;
17 : 5008;
18 : 5028;
19 : 284F;
20 : 43F1;
21 : 3568;
22 : 45F5;
23 : 484D;
24 : 8806;
25 : 0040;
26 : B800;
27 : 8807;
28 : 085A;
29 : B800;
30 : 8808;
31 : 0A6F;
32 : B800;
33 : 8809;
34 : 0C53;
35 : B801;
36 : 880A;
37 : B00B;
38 : 0E70;
39 : B800;
40 : 880C;
41 : 1063;
42 : B800;
43 : 880D;
44 : 126D;
45 : B800;
46 : 880E;
47 : 147A;
48 : B800;
49 : 880F;
50 : 5340;
51 : 53C0;
52 : 1660;
53 : B801;
54 : 1863;
55 : 1A5A;
56 : 1FB8;
57 : 7C00;
58 : 1C6F;
59 : 204C;
60 : A810;
61 : 226D;
62 : 246D;
63 : 8805;
64 : 5488;
65 : 5698;
66 : A028;
67 : 7E00;
[68..2047] : 0000;
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END;