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10 lines
1.1 KiB
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# StackSynth - Final Project
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This repository contains the source files and notes from my Final Project, as part of my Masters of Engineering in Electronics and Information Engineering at Imperial College London.
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StackSynth is an educational synthesizer platform based on the STM32L432, used in the 3rd Year Embedded Systems module, with lab notes available on the [GitHub repository](https://github.com/edstott/ES-synth-starter). The ARM Cortex-M4 based CPU is not optimised for the Digital Signal Processing operations needed for complex audio waveform generation.
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The goal of this project was to create the SystemVerilog modules and code for an FPGA-based extension module for StackSynth, to increase the audio ability and performance of the synthesizer while providing future Embedded Systems students an opportunity to develop code for an integrated [VexRiscV](https://github.com/SpinalHDL/VexRiscv) RISC-V System-on-Chip.
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Notes taken during this project primarily consist of links for useful reading and reference materials, and is available in [this document](./notes/readme.md).
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