Aadi Desai
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fd53e3c579
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Move sine bit inversion from genSaw to saw2sin
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2023-06-06 18:51:36 +01:00 |
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Aadi Desai
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47574015e4
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Remove unused files
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2023-06-05 13:52:59 +01:00 |
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Aadi Desai
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aac2ad4c62
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Add always_ff in saw2sin to fix glitches
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2023-06-04 14:14:05 +01:00 |
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Aadi Desai
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743c9fdb64
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Create CAN RX block, ACKs frames, no TX
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2023-06-04 12:38:39 +01:00 |
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Aadi Desai
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4b57bdfa80
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Update cordic.sv and saw2sin.sv for better accuracy, genSaw.sv to fix polarity of tri/sin
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2023-06-04 12:07:28 +01:00 |
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Aadi Desai
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d784f6d251
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Add sine wave generator using cordic
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2023-05-28 16:07:23 +01:00 |
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Aadi Desai
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6601b6f3af
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Add quarter wave cordic block
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2023-05-28 16:06:49 +01:00 |
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Aadi Desai
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bb94e58a53
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Completed dacVolume.sv, issues remain
If dacVolume and testSaw are instantiated in the same design, the design fails to run
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2023-05-22 13:28:14 +01:00 |
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Aadi Desai
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275a74013c
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Create volume control module, not functional
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2023-05-21 01:22:39 +01:00 |
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Aadi Desai
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c4469cd6f6
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Flip MSB of square wave, avoid DAC automute
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2023-05-18 16:19:53 +01:00 |
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Aadi Desai
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6381cb53a8
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Optimise triangle wave gen and add comments
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2023-05-18 12:42:09 +01:00 |
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Aadi Desai
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a17429c105
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Support selecting waveform in genSaw
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2023-05-18 12:35:39 +01:00 |
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Aadi Desai
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81cf1ebc5c
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Replace assign with always_comb in rtl/
Update to better match IEEE1800-2017
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2023-05-18 12:01:56 +01:00 |
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Aadi Desai
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06fc184cc5
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Working version of dac driver
Output limited to 16bit as the set bitclock rate is too low for 24bit
Main work was on timing issues and inconsistent output
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2023-05-16 22:12:41 +01:00 |
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Aadi Desai
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0ce0835a45
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Working version of sample generator
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2023-05-16 22:11:17 +01:00 |
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Aadi Desai
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5b66d01ac6
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Add comments to sawtooth generator
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2023-05-12 14:00:13 +01:00 |
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Aadi Desai
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3edc1f92d7
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Add DAC Driver block
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2023-03-11 18:05:03 +00:00 |
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Aadi Desai
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a473a6ff9c
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Add Sawtooth Generator Block
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2023-03-11 18:04:53 +00:00 |
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Aadi Desai
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0f61a6d19a
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Add pcmfifo SystemVerilog module
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2023-03-10 17:47:39 +00:00 |
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Aadi Desai
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529efcaf9f
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Add pwm module to set LED colour from LiteX Console
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2023-03-03 17:05:00 +00:00 |
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Aadi Desai
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d960053a7e
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Update flip.sv to cycle across colours using 48MHz
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2023-03-03 17:04:22 +00:00 |
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Aadi Desai
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e1b0d5c28c
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Add testing SystemVerilog and LiteX Module
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2023-02-26 19:40:56 +00:00 |
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