EIE4-FYP/rtl
2023-06-04 14:14:05 +01:00
..
can.sv Create CAN RX block, ACKs frames, no TX 2023-06-04 12:38:39 +01:00
cordic.sv Update cordic.sv and saw2sin.sv for better accuracy, genSaw.sv to fix polarity of tri/sin 2023-06-04 12:07:28 +01:00
dacDriver.sv Working version of dac driver 2023-05-16 22:12:41 +01:00
dacVolume.sv Completed dacVolume.sv, issues remain 2023-05-22 13:28:14 +01:00
flip.sv Replace assign with always_comb in rtl/ 2023-05-18 12:01:56 +01:00
flipPwm.sv Replace assign with always_comb in rtl/ 2023-05-18 12:01:56 +01:00
genSaw.sv Add always_ff in saw2sin to fix glitches 2023-06-04 14:14:05 +01:00
pcmfifo.sv Add pcmfifo SystemVerilog module 2023-03-10 17:47:39 +00:00
saw2sin.sv Add always_ff in saw2sin to fix glitches 2023-06-04 14:14:05 +01:00