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Aadi Desai
6475de9495
test_saw2sin.py: cocotb testbench using verilator cordic.sv: o_sin adjustments mask erratic results at extremes, avg error is 1.346 vs testbench
10 lines
302 B
Makefile
10 lines
302 B
Makefile
SIM ?= verilator
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TOPLEVEL_LANG ?= verilog
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VERILOG_SOURCES += $(PWD)/saw2sin.sv $(PWD)/cordic.sv
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TOPLEVEL = saw2sin
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MODULE = test_saw2sin
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EXTRA_ARGS += --trace-fst --trace-structs
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# include cocotb's make rules to take care of the simulator setup
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include $(shell cocotb-config --makefiles)/Makefile.sim
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