cordic/Makefile

SIM ?= verilator
TOPLEVEL_LANG ?= verilog
VERILOG_SOURCES += $(PWD)/saw2sin.sv $(PWD)/cordic.sv
TOPLEVEL = saw2sin
MODULE = test_saw2sin
EXTRA_ARGS += --trace-fst --trace-structs

# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim
Add cordic.sv and test_saw2sin.py test_saw2sin.py: cocotb testbench using verilator cordic.sv: o_sin adjustments mask erratic results at extremes, avg error is 1.346 vs testbench 2023-05-28 15:15:56 +00:00			`SIM ?= verilator`
			`TOPLEVEL_LANG ?= verilog`
			`VERILOG_SOURCES += $(PWD)/saw2sin.sv $(PWD)/cordic.sv`
			`TOPLEVEL = saw2sin`
			`MODULE = test_saw2sin`
			`EXTRA_ARGS += --trace-fst --trace-structs`

			`# include cocotb's make rules to take care of the simulator setup`
			`include $(shell cocotb-config --makefiles)/Makefile.sim`