mirror of
https://github.com/supleed2/apbDriver.git
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77 lines
2.1 KiB
Systemverilog
77 lines
2.1 KiB
Systemverilog
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// SystemVerilog testbench to instantiate Driver and Slave modules
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// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/* verilator lint_off UNUSED */
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module apbTest
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( input var logic i_clk
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, input var logic i_rst
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, input var logic i_arst
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);
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localparam int unsigned AddrWidth = 12;
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localparam int unsigned DataWidth = 32;
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localparam int unsigned StrbWidth = 4;
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logic i_rst_n;
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assign i_rst_n = !i_rst;
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logic o_ck;
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assign apbBus.ckApb = o_ck;
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apbSlave
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#(.AWIDTH (AddrWidth )
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, .DWIDTH (DataWidth )
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, .SWIDTH (StrbWidth )
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) u_apbSlave
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( .i_ck (apbBus.ckApb )
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, .i_rst_n (i_rst_n )
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, .i_sel (apbBus.apbPSel )
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, .i_enable (apbBus.apbPEnable)
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, .i_addr (apbBus.apbPAddr )
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, .i_write (apbBus.apbPWrite )
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, .i_wdata (apbBus.apbPWData )
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, .i_strb (apbBus.apbPStrb )
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, .i_prot (apbBus.apbPProt )
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, .o_rdata (apbBus.apbPRData )
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, .o_ready (apbBus.apbPReady )
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, .o_slverr (apbBus.apbPSlvErr)
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);
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generateClock u_generateClock
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( .o_clk (o_ck ) // Generated clock for testbench
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, .i_rootClk (i_clk) // V_erilator clock input
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, .i_periodHi (0 ) // Number of rootClk cycles-1 to stay high
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, .i_periodLo (0 ) // Number of rootClk cycles-1 to stay low
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, .i_jitterControl (0 ) // Random jitter control (0: none --> higher number: more jitter)
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);
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in_ApbBus
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#(.APB_DW (DataWidth)
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, .APB_AW (AddrWidth)
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) apbBus ();
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ApbDriver
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#(.APB_AW (AddrWidth )
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, .APB_DW (DataWidth )
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, .APB_SW (StrbWidth )
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) u_apbDriver
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( .ckApb (apbBus.ckApb )
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, .apbPRData (apbBus.apbPRData )
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, .apbPReady (apbBus.apbPReady )
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, .apbPSlvErr (apbBus.apbPSlvErr)
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, .apbPSel (apbBus.apbPSel )
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, .apbPEnable (apbBus.apbPEnable)
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, .apbPAddr (apbBus.apbPAddr )
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, .apbPWrite (apbBus.apbPWrite )
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, .apbPWData (apbBus.apbPWData )
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, .apbPStrb (apbBus.apbPStrb )
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, .apbPProt (apbBus.apbPProt )
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);
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endmodule
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/* verilator lint_on UNUSED */
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`resetall
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