supleed2/apbDriver
1
0
Fork 0
mirror of https://github.com/supleed2/apbDriver.git synced 2024-12-22 05:35:48 +00:00
Code Issues Packages Projects Releases Wiki Activity

Initial Commit

Browse source
This commit is contained in:
Aadi Desai 2022-09-15 18:28:16 +01:00
commit 19f7e14cd9
No known key found for this signature in database
GPG key ID: CFFFE425830EF4D9
12 changed files with 1027 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.gitattributes vendored Normal file
View file

@ -0,0 +1,2 @@
# Auto detect text files and perform LF normalization
* text=auto

1
.gitignore vendored Normal file
View file

@ -0,0 +1 @@
/output/

293
ApbDriver.sv Normal file
View file

@ -0,0 +1,293 @@
// Synthesizable DPI-C driver for APB Bus Interface
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
// Example Usage:
// ### test_DUT.sv (Instance) ###
// ApbDriver
// #(.APB_AW (32)
// , .APB_DW (32)
// , .APB_SW ( 4)
// ) u_apbDriver
// ( .ckApb (apbBus.ckApb )
// , .apbPRData (apbBus.apbPRData )
// , .apbPReady (apbBus.apbPReady )
// , .apbPSlvErr (apbBus.apbPSlvErr)
// , .apbPSel (apbBus.apbPSel )
// , .apbPEnable (apbBus.apbPEnable)
// , .apbPAddr (apbBus.apbPAddr )
// , .apbPWrite (apbBus.apbPWrite )
// , .apbPWData (apbBus.apbPWData )
// , .apbPStrb (apbBus.apbPStrb )
// , .apbPProt (apbBus.apbPProt )
// );
// ### test_DUT.cpp (Setup) ###
// #include <Vtest_DUT__Dpi.h>
// EITHER: VerilatorTbFst<Vtest_DUT>* tb = new VerilatorTbFst<Vtest_DUT>();
// OR : VerilatorTbVcd<Vtest_DUT>* tb = new VerilatorTbVcd<Vtest_DUT>();
// tb->setScope("test_DUT.u_apbDriver");
// ### test_DUT.cpp (Usage) ###
// uint32_t addr = 0x0100, data = 0x1234, strb = 0b1111, prot = 0b110;
// int err = 0;
// uint8_t SlvErr = 0;
// uint32_t readData = 0;
// err = tryStartApbWrite(&addr, &data, &strb, &prot);
// if (err != 0) { printf("tryStartApbWrite failed!\n"); }
// else {
// tb->ticks(2);
// err = tryFinishApbWrite(&SlvErr);
// while (err != 0) {
// printf("tryFinishApbWrite failed!\n");
// tb->tick();
// err = tryFinishApbWrite(&SlvErr);
// }
// if (SlvErr != 0) { printf("Apb Write failed!\n"); }
// }
// tb->tick();
// err = tryStartApbRead(&addr, &prot);
// if (err != 0) { printf("tryStartApbRead failed!\n"); }
// else {
// tb->ticks(2);
// err = tryFinishApbRead(&SlvErr, &readData);
// while (err != 0) {
// printf("tryFinishApbRead failed!\n");
// tb->tick();
// err = tryFinishApbRead(&SlvErr, &readData);
// }
// if (SlvErr != 0) { printf("Apb Read failed!\n"); }
// else { printf("Apb Read succeeded!\nExpected Read Data: 0x%x\nReceived Read Data: 0x%x\n", data, readData); }
// }
// tb->tick();
module ApbDriver
#(parameter int unsigned APB_AW = 32 // APB Address Width
, parameter int unsigned APB_DW = 32 // APB Data Width
, parameter int unsigned APB_SW = APB_DW/8 // APB Write Strobe Width
)(input var logic ckApb // -- Inputs to Driver
, input var logic [APB_DW-1:0] apbPRData
, input var logic apbPReady
, input var logic apbPSlvErr
, output var logic apbPSel // -- Outputs from Driver
, output var logic apbPEnable
, output var logic [APB_AW-1:0] apbPAddr
, output var logic apbPWrite
, output var logic [APB_DW-1:0] apbPWData
, output var logic [APB_SW-1:0] apbPStrb
, output var logic [2:0] apbPProt
);
// Delay-based version, does not allow for other accesses in C++ testbench
// while task is running, synthesizable version below is preferred
/*
export "DPI-C" task apbRead;
export "DPI-C" task apbWrite;
logic trComplete;
assign trComplete = ckApb & apbPReady;
task automatic apbRead (input bit [APB_AW-1:0] addr, input bit [2:0] prot, output bit SlvErr, output bit [APB_DW-1:0] RData);
@(posedge ckApb);
apbPSel = '1;
apbPEnable = '0;
apbPAddr = addr;
apbPWrite = '0;
apbPStrb = '0;
apbPProt = prot;
@(posedge ckApb);
apbPEnable = '1;
@(posedge trComplete);
apbPSel = '0;
RData = apbPRData;
SlvErr = apbPSlvErr;
endtask
task automatic apbWrite (input bit [APB_AW-1:0] addr, input bit [APB_DW-1:0] data, input bit [APB_SW-1:0] strb, input bit [2:0] prot, output bit SlvErr);
@(posedge ckApb);
apbPSel = '1;
apbPEnable = '0;
apbPAddr = addr;
apbPWrite = '1;
apbPWData = data;
apbPStrb = strb;
apbPProt = prot;
@(posedge ckApb);
apbPEnable = '1;
@(posedge trComplete);
apbPSel = '0;
SlvErr = apbPSlvErr;
endtask
*/
// Returns 0 if complete and -1 if bus was busy / not ready yet
export "DPI-C" function tryStartApbRead;
export "DPI-C" function tryStartApbWrite;
export "DPI-C" function tryFinishApbRead;
export "DPI-C" function tryFinishApbWrite;
enum bit [2:0]
{ IDLE
, R_SETUP
, R_ACCESS
, W_SETUP
, W_ACCESS
} apbState;
enum bit [1:0]
{ n_NONE
, n_IDLE
, n_READ
, n_WRITE
} nextState;
logic [APB_AW-1:0] nextAddr;
logic [APB_DW-1:0] nextWData;
logic [APB_SW-1:0] nextStrb;
logic [2:0] nextProt;
always_ff @(posedge ckApb) // apbPSel
case (apbState)
IDLE: apbPSel <= '0;
R_SETUP: apbPSel <= '1;
R_ACCESS: apbPSel <= '1;
W_SETUP: apbPSel <= '1;
W_ACCESS: apbPSel <= '1;
default: apbPSel <= '0;
endcase
always_ff @(posedge ckApb) // apbPEnable
case (apbState)
IDLE: apbPEnable <= '0;
R_SETUP: apbPEnable <= '0;
R_ACCESS: apbPEnable <= '1;
W_SETUP: apbPEnable <= '0;
W_ACCESS: apbPEnable <= '1;
default: apbPEnable <= '0;
endcase
always_ff @(posedge ckApb) // apbPAddr
case (apbState)
IDLE: apbPAddr <= '0;
R_SETUP: apbPAddr <= nextAddr;
R_ACCESS: apbPAddr <= nextAddr;
W_SETUP: apbPAddr <= nextAddr;
W_ACCESS: apbPAddr <= nextAddr;
default: apbPAddr <= '0;
endcase
always_ff @(posedge ckApb) // apbPWrite
case (apbState)
IDLE: apbPWrite <= '0;
R_SETUP: apbPWrite <= '0;
R_ACCESS: apbPWrite <= '0;
W_SETUP: apbPWrite <= '1;
W_ACCESS: apbPWrite <= '1;
default: apbPWrite <= '0;
endcase
always_ff @(posedge ckApb) // apbPWData
case (apbState)
IDLE: apbPWData <= '0;
R_SETUP: apbPWData <= '0;
R_ACCESS: apbPWData <= '0;
W_SETUP: apbPWData <= nextWData;
W_ACCESS: apbPWData <= nextWData;
default: apbPWData <= '0;
endcase
always_ff @(posedge ckApb) // apbPStrb
case (apbState)
IDLE: apbPStrb <= '0;
R_SETUP: apbPStrb <= '0;
R_ACCESS: apbPStrb <= '0;
W_SETUP: apbPStrb <= nextStrb;
W_ACCESS: apbPStrb <= nextStrb;
default: apbPStrb <= '0;
endcase
always_ff @(posedge ckApb) // apbPProt
case (apbState)
IDLE: apbPProt <= '0;
R_SETUP: apbPProt <= nextProt;
R_ACCESS: apbPProt <= nextProt;
W_SETUP: apbPProt <= nextProt;
W_ACCESS: apbPProt <= nextProt;
default: apbPProt <= '0;
endcase
always_ff @(posedge ckApb) // apbState
case (apbState)
IDLE: if (nextState == n_READ) apbState <= R_SETUP;
else if (nextState == n_WRITE) apbState <= W_SETUP;
else apbState <= IDLE;
R_SETUP: apbState <= R_ACCESS;
R_ACCESS: if (nextState == n_IDLE) apbState <= IDLE;
else apbState <= R_ACCESS;
W_SETUP: apbState <= W_ACCESS;
W_ACCESS: if (nextState == n_IDLE) apbState <= IDLE;
else apbState <= W_ACCESS;
default: apbState <= IDLE;
endcase
function automatic int tryStartApbRead (input bit [APB_AW-1:0] addr, input bit [2:0] prot);
if (apbState == IDLE && (nextState == n_NONE || nextState == n_IDLE)) begin
nextAddr = addr;
nextWData = '0;
nextStrb = '0;
nextProt = prot;
nextState = n_READ;
return 0;
end else
return -1;
endfunction
function automatic int tryStartApbWrite (input bit [APB_AW-1:0] addr, input bit [APB_DW-1:0] data, input bit [APB_SW-1:0] strb, input bit [2:0] prot);
if (apbState == IDLE && (nextState == n_NONE || nextState == n_IDLE)) begin
nextAddr = addr;
nextWData = data;
nextStrb = strb;
nextProt = prot;
nextState = n_WRITE;
return 0;
end else
return -1;
endfunction
function automatic int tryFinishApbRead (output bit SlvErr, output bit [APB_DW-1:0] RData);
if (apbState == R_ACCESS && apbPReady) begin
nextAddr = '0;
nextWData = '0;
nextStrb = '0;
nextProt = '0;
SlvErr = apbPSlvErr;
RData = apbPRData;
nextState = n_IDLE;
return 0;
end else
return -1;
endfunction
function automatic int tryFinishApbWrite (output bit SlvErr);
if (apbState == W_ACCESS && apbPReady) begin
nextAddr = '0;
nextWData = '0;
nextStrb = '0;
nextProt = '0;
SlvErr = apbPSlvErr;
nextState = n_IDLE;
return 0;
end else
return -1;
endfunction
endmodule
`resetall

201
LICENSE Normal file
View file

@ -0,0 +1,201 @@
Apache License
Version 2.0, January 2004
<http://www.apache.org/licenses/>
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions.
"License" shall mean the terms and conditions for use, reproduction,
and distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the copyright owner or entity authorized by
the copyright owner that is granting the License.
"Legal Entity" shall mean the union of the acting entity and all
other entities that control, are controlled by, or are under common
control with that entity. For the purposes of this definition,
"control" means (i) the power, direct or indirect, to cause the
direction or management of such entity, whether by contract or
otherwise, or (ii) ownership of fifty percent (50%) or more of the
outstanding shares, or (iii) beneficial ownership of such entity.
"You" (or "Your") shall mean an individual or Legal Entity
exercising permissions granted by this License.
"Source" form shall mean the preferred form for making modifications,
including but not limited to software source code, documentation
source, and configuration files.
"Object" form shall mean any form resulting from mechanical
transformation or translation of a Source form, including but
not limited to compiled object code, generated documentation,
and conversions to other media types.
"Work" shall mean the work of authorship, whether in Source or
Object form, made available under the License, as indicated by a
copyright notice that is included in or attached to the work
(an example is provided in the Appendix below).
"Derivative Works" shall mean any work, whether in Source or Object
form, that is based on (or derived from) the Work and for which the
editorial revisions, annotations, elaborations, or other modifications
represent, as a whole, an original work of authorship. For the purposes
of this License, Derivative Works shall not include works that remain
separable from, or merely link (or bind by name) to the interfaces of,
the Work and Derivative Works thereof.
"Contribution" shall mean any work of authorship, including
the original version of the Work and any modifications or additions
to that Work or Derivative Works thereof, that is intentionally
submitted to Licensor for inclusion in the Work by the copyright owner
or by an individual or Legal Entity authorized to submit on behalf of
the copyright owner. For the purposes of this definition, "submitted"
means any form of electronic, verbal, or written communication sent
to the Licensor or its representatives, including but not limited to
communication on electronic mailing lists, source code control systems,
and issue tracking systems that are managed by, or on behalf of, the
Licensor for the purpose of discussing and improving the Work, but
excluding communication that is conspicuously marked or otherwise
designated in writing by the copyright owner as "Not a Contribution."
"Contributor" shall mean Licensor and any individual or Legal Entity
on behalf of whom a Contribution has been received by Licensor and
subsequently incorporated within the Work.
2. Grant of Copyright License. Subject to the terms and conditions of
this License, each Contributor hereby grants to You a perpetual,
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
copyright license to reproduce, prepare Derivative Works of,
publicly display, publicly perform, sublicense, and distribute the
Work and such Derivative Works in Source or Object form.
3. Grant of Patent License. Subject to the terms and conditions of
this License, each Contributor hereby grants to You a perpetual,
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
(except as stated in this section) patent license to make, have made,
use, offer to sell, sell, import, and otherwise transfer the Work,
where such license applies only to those patent claims licensable
by such Contributor that are necessarily infringed by their
Contribution(s) alone or by combination of their Contribution(s)
with the Work to which such Contribution(s) was submitted. If You
institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the Work
or a Contribution incorporated within the Work constitutes direct
or contributory patent infringement, then any patent licenses
granted to You under this License for that Work shall terminate
as of the date such litigation is filed.
4. Redistribution. You may reproduce and distribute copies of the
Work or Derivative Works thereof in any medium, with or without
modifications, and in Source or Object form, provided that You
meet the following conditions:
(a) You must give any other recipients of the Work or
Derivative Works a copy of this License; and
(b) You must cause any modified files to carry prominent notices
stating that You changed the files; and
(c) You must retain, in the Source form of any Derivative Works
that You distribute, all copyright, patent, trademark, and
attribution notices from the Source form of the Work,
excluding those notices that do not pertain to any part of
the Derivative Works; and
(d) If the Work includes a "NOTICE" text file as part of its
distribution, then any Derivative Works that You distribute must
include a readable copy of the attribution notices contained
within such NOTICE file, excluding those notices that do not
pertain to any part of the Derivative Works, in at least one
of the following places: within a NOTICE text file distributed
as part of the Derivative Works; within the Source form or
documentation, if provided along with the Derivative Works; or,
within a display generated by the Derivative Works, if and
wherever such third-party notices normally appear. The contents
of the NOTICE file are for informational purposes only and
do not modify the License. You may add Your own attribution
notices within Derivative Works that You distribute, alongside
or as an addendum to the NOTICE text from the Work, provided
that such additional attribution notices cannot be construed
as modifying the License.
You may add Your own copyright statement to Your modifications and
may provide additional or different license terms and conditions
for use, reproduction, or distribution of Your modifications, or
for any such Derivative Works as a whole, provided Your use,
reproduction, and distribution of the Work otherwise complies with
the conditions stated in this License.
5. Submission of Contributions. Unless You explicitly state otherwise,
any Contribution intentionally submitted for inclusion in the Work
by You to the Licensor shall be under the terms and conditions of
this License, without any additional terms or conditions.
Notwithstanding the above, nothing herein shall supersede or modify
the terms of any separate license agreement you may have executed
with Licensor regarding such Contributions.
6. Trademarks. This License does not grant permission to use the trade
names, trademarks, service marks, or product names of the Licensor,
except as required for reasonable and customary use in describing the
origin of the Work and reproducing the content of the NOTICE file.
7. Disclaimer of Warranty. Unless required by applicable law or
agreed to in writing, Licensor provides the Work (and each
Contributor provides its Contributions) on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
implied, including, without limitation, any warranties or conditions
of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
PARTICULAR PURPOSE. You are solely responsible for determining the
appropriateness of using or redistributing the Work and assume any
risks associated with Your exercise of permissions under this License.
8. Limitation of Liability. In no event and under no legal theory,
whether in tort (including negligence), contract, or otherwise,
unless required by applicable law (such as deliberate and grossly
negligent acts) or agreed to in writing, shall any Contributor be
liable to You for damages, including any direct, indirect, special,
incidental, or consequential damages of any character arising as a
result of this License or out of the use or inability to use the
Work (including but not limited to damages for loss of goodwill,
work stoppage, computer failure or malfunction, or any and all
other commercial damages or losses), even if such Contributor
has been advised of the possibility of such damages.
9. Accepting Warranty or Additional Liability. While redistributing
the Work or Derivative Works thereof, You may choose to offer,
and charge a fee for, acceptance of support, warranty, indemnity,
or other liability obligations and/or rights consistent with this
License. However, in accepting such obligations, You may act only
on Your own behalf and on Your sole responsibility, not on behalf
of any other Contributor, and only if You agree to indemnify,
defend, and hold each Contributor harmless for any liability
incurred by, or claims asserted against, such Contributor by reason
of your accepting any such warranty or additional liability.
END OF TERMS AND CONDITIONS
APPENDIX: How to apply the Apache License to your work.
To apply the Apache License to your work, attach the following
boilerplate notice, with the fields enclosed by brackets "[]"
replaced with your own identifying information. (Don't include
the brackets!) The text should be enclosed in the appropriate
comment syntax for the file format. We also recommend that a
file or class name and description of purpose be included on the
same "printed page" as the copyright notice for easier
identification within third-party archives.
Copyright 2022 Aadi Desai
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.

5
README.md Normal file
View file

@ -0,0 +1,5 @@
# apbDriver
Basic APB-compatible module designed for use with Verilator, but should work with any DPI-C compatible simulator.
The module allows for transactions to be started and stopped from within the C++ testbench, and functions execute in 0 time. Transactions cannot be queued but the function return code indicates success, so time can be advanced and the transaction attempted again in the case of failure.

136
VerilatorTbFst.h Normal file
View file

@ -0,0 +1,136 @@
// Header file to be used in verilator C++ testbenches.
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
//
// Intended usage / order:
// - VerilatorTbFst<Vtest_DUT> *tb = new VerilatorTbFst<Vtest_DUT>();
// - tb->setClockPeriodPS(clock_period_in_picoseconds);
// - This value can be taken from within the SystemVerilog Testbench
// - tb->opentrace("output/test_DUT.verilator.fst");
// - tb->m_trace->dump(0);
// - Followed by arst/rst and signals matching the intended testbench flow.
#ifndef _VERILATORTBFST_H
#define _VERILATORTBFST_H
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <svdpi.h>
#include <verilated_fst_c.h>
typedef enum {
ERROR,
WARN,
NOTE
} TbPrintLevel;
template <class VA>
class VerilatorTbFst {
public:
VA *m_dut;
VerilatedFstC *m_trace;
uint64_t m_tickcount;
uint64_t m_clockperiod;
bool m_dodump;
VerilatorTbFst(void) : m_trace(NULL), m_tickcount(0l) {
m_dut = new VA;
Verilated::traceEverOn(true);
m_dut->i_clk = 0;
m_dut->i_rst = 1;
m_dodump = true;
eval(); // Get our initial values set properly.
}
virtual ~VerilatorTbFst(void) {
closetrace();
delete m_dut;
m_dut = NULL;
}
virtual void setClockPeriodPS(const uint64_t ps) {
m_clockperiod = ps;
}
virtual void opentrace(const char *fstname) {
opentrace(fstname, 99);
}
virtual void opentrace(const char *fstname, int tracedepth) {
if (!m_trace) {
m_trace = new VerilatedFstC;
m_dut->trace(m_trace, tracedepth);
m_trace->open(fstname);
}
}
virtual void closetrace(void) {
if (m_trace) {
m_trace->close();
delete m_trace;
m_trace = NULL;
}
}
virtual void eval(void) {
m_dut->eval();
}
// Call from loop {check, drive, tick}
virtual void tick(void) {
// check
// drive
// rise eval dump
// fall eval dump
m_dut->i_clk = 1;
eval();
if (m_dodump && m_trace) {
m_trace->dump((uint64_t)(m_clockperiod * m_tickcount));
}
m_dut->i_clk = 0;
eval();
if (m_dodump && m_trace) {
m_trace->dump((uint64_t)(m_clockperiod * m_tickcount + (m_clockperiod / 2)));
m_trace->flush();
}
m_tickcount++;
}
virtual void ticks(int numTicks) {
for (int i = 0; i < numTicks; i++)
tick();
}
virtual void areset(void) {
m_dut->i_arst = 0;
tick();
m_dut->i_arst = 1;
ticks(4);
m_dut->i_arst = 0;
}
virtual void reset(void) {
m_dut->i_rst = 1;
ticks(5);
m_dut->i_rst = 0;
}
unsigned long tickcount(void) {
return m_tickcount;
}
virtual bool done(void) {
return Verilated::gotFinish();
}
virtual void setScope(const char *scopeName) {
char fullScopeName[1024];
svSetScope(svGetScopeFromName(strcat(strcpy(fullScopeName, "TOP."), scopeName)));
}
};
#endif // _VERILATORTBFST_H

75
apbSlave.sv Normal file
View file

@ -0,0 +1,75 @@
// Example APB Slave for testing APB Driver module
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/* verilator lint_off UNUSED */
module apbSlave
#(parameter int AWIDTH = 12
, parameter int DWIDTH = 32
, parameter int SWIDTH = DWIDTH/8
)(input var logic i_ck
, input var logic i_rst_n
, input var logic i_sel
, input var logic i_enable
, input var logic [AWIDTH-1:0] i_addr
, input var logic i_write
, input var logic [DWIDTH-1:0] i_wdata
, input var logic [SWIDTH-1:0] i_strb
, input var logic [2:0] i_prot
, output var logic [DWIDTH-1:0] o_rdata
, output var logic o_ready
, output var logic o_slverr
);
logic [DWIDTH-1:0] mem [4096];
logic [DWIDTH-1:0] wdata;
for (genvar i = 0; i < SWIDTH; i++) begin
assign wdata[8*i+7:8*i] = i_strb[i] ? i_wdata[8*i+7:8*i] : mem[i_addr][8*i+7:8*i];
end
enum bit [1:0]
{ SETUP
, WRITE
, READ
} STATE;
always_comb
case (STATE)
SETUP: begin
o_rdata = '0;
o_ready = '0;
o_slverr = '0;
end
WRITE: begin
o_rdata = '0;
o_ready = '1;
o_slverr = '0;
end
READ: begin
o_rdata = mem[i_addr];
o_ready = '1;
o_slverr = '0;
end
default: begin end
endcase
always_ff @(posedge i_ck)
if (i_rst_n == 0)
STATE <= SETUP;
else if (i_sel == 0)
STATE <= SETUP;
else
if (i_write == 0)
STATE <= READ;
else
STATE <= WRITE;
always_ff @(negedge i_ck)
if (STATE == WRITE) mem[i_addr] <= wdata;
else mem[i_addr] <= mem[i_addr];
endmodule
/* verilator lint_on UNUSED */
`resetall

141
apbTest.cpp Normal file
View file

@ -0,0 +1,141 @@
// Verilator testbench for testing the APB Driver
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
#include "VerilatorTbFst.h"
#include <VapbTest.h>
#include <VapbTest__Dpi.h>
#include <iostream>
#include <stdlib.h>
#include <string>
#include <svdpi.h>
#include <verilated.h>
#ifndef N_CYCLES
#define N_CYCLES 100
#endif
int main(int argc, char **argv, char **env) {
Verilated::commandArgs(argc, argv);
VerilatorTbFst<VapbTest> *tb = new VerilatorTbFst<VapbTest>();
tb->setScope("apbTest.u_apbDriver");
// Get SystemVerilog Parameters
const uint64_t CLOCK_PERIOD_PS = 10;
tb->setClockPeriodPS(2 * (CLOCK_PERIOD_PS / 3));
tb->opentrace("output/VapbTest.fst");
tb->m_trace->dump(0); // Initialize waveform at beginning of time.
printf("Starting!\n");
tb->m_dut->i_rst = 1;
tb->ticks(2);
tb->m_dut->i_rst = 0;
tb->ticks(2);
uint32_t addr, data, strb, prot;
int err = 0;
uint8_t SlvErr = 0;
uint32_t readData = 0;
addr = 0x100u;
data = 0x1234BEEFu;
strb = 0b1111u;
prot = 0b110u;
err = tryStartApbWrite(&addr, &data, &strb, &prot);
if (err != 0) {
printf("tryStartApbWrite failed!\n");
} else {
printf("tryStartApbWrite succeeded!\n");
tb->ticks(2);
err = tryFinishApbWrite(&SlvErr);
while (err != 0) {
printf("tryFinishApbWrite failed!\n");
tb->tick();
err = tryFinishApbWrite(&SlvErr);
}
printf("tryFinishApbWrite succeeded!\n");
if (SlvErr != 0) {
printf("Apb Write failed!\n");
} else {
printf("Apb Write succeeded!\n");
}
}
tb->tick();
tb->tick();
err = tryStartApbRead(&addr, &prot);
if (err != 0) {
printf("tryStartApbRead failed!\n");
} else {
printf("tryStartApbRead succeeded!\n");
tb->ticks(2);
err = tryFinishApbRead(&SlvErr, &readData);
while (err != 0) {
printf("tryFinishApbRead failed!\n");
tb->tick();
err = tryFinishApbRead(&SlvErr, &readData);
}
printf("tryFinishApbRead succeeded!\n");
if (SlvErr != 0) {
printf("Apb Read failed!\n");
} else {
printf("Apb Read succeeded!\nReceived Read Data: 0x%x\n", readData);
}
}
tb->tick();
tb->tick();
data = 0xDEAD5678u;
strb = 0b1100u;
err = tryStartApbWrite(&addr, &data, &strb, &prot);
if (err != 0) {
printf("tryStartApbWrite failed!\n");
} else {
printf("tryStartApbWrite succeeded!\n");
tb->ticks(2);
err = tryFinishApbWrite(&SlvErr);
while (err != 0) {
printf("tryFinishApbWrite failed!\n");
tb->tick();
err = tryFinishApbWrite(&SlvErr);
}
printf("tryFinishApbWrite succeeded!\n");
if (SlvErr != 0) {
printf("Apb Write failed!\n");
} else {
printf("Apb Write succeeded!\n");
}
}
tb->tick();
tb->tick();
err = tryStartApbRead(&addr, &prot);
if (err != 0) {
printf("tryStartApbRead failed!\n");
} else {
printf("tryStartApbRead succeeded!\n");
tb->ticks(2);
err = tryFinishApbRead(&SlvErr, &readData);
while (err != 0) {
printf("tryFinishApbRead failed!\n");
tb->tick();
err = tryFinishApbRead(&SlvErr, &readData);
}
printf("tryFinishApbRead succeeded!\n");
if (SlvErr != 0) {
printf("Apb Read failed!\n");
} else {
printf("Apb Read succeeded!\nExpected Read Data: 0x%x\nReceived Read Data: 0x%x\n", 0xDEADBEEFu, readData);
}
}
tb->tick();
tb->tick();
while (tb->tickcount() < N_CYCLES * 2) {
tb->ticks(2); // Run Tests
}
printf("Time: %ldns\n", tb->tickcount());
printf("Stopped.\n");
tb->closetrace();
exit(EXIT_SUCCESS);
}

76
apbTest.sv Normal file
View file

@ -0,0 +1,76 @@
// SystemVerilog testbench to instantiate Driver and Slave modules
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/* verilator lint_off UNUSED */
module apbTest
( input var logic i_clk
, input var logic i_rst
, input var logic i_arst
);
localparam int unsigned AddrWidth = 12;
localparam int unsigned DataWidth = 32;
localparam int unsigned StrbWidth = 4;
logic i_rst_n;
assign i_rst_n = !i_rst;
logic o_ck;
assign apbBus.ckApb = o_ck;
apbSlave
#(.AWIDTH (AddrWidth )
, .DWIDTH (DataWidth )
, .SWIDTH (StrbWidth )
) u_apbSlave
( .i_ck (apbBus.ckApb )
, .i_rst_n (i_rst_n )
, .i_sel (apbBus.apbPSel )
, .i_enable (apbBus.apbPEnable)
, .i_addr (apbBus.apbPAddr )
, .i_write (apbBus.apbPWrite )
, .i_wdata (apbBus.apbPWData )
, .i_strb (apbBus.apbPStrb )
, .i_prot (apbBus.apbPProt )
, .o_rdata (apbBus.apbPRData )
, .o_ready (apbBus.apbPReady )
, .o_slverr (apbBus.apbPSlvErr)
);
generateClock u_generateClock
( .o_clk (o_ck ) // Generated clock for testbench
, .i_rootClk (i_clk) // V_erilator clock input
, .i_periodHi (0 ) // Number of rootClk cycles-1 to stay high
, .i_periodLo (0 ) // Number of rootClk cycles-1 to stay low
, .i_jitterControl (0 ) // Random jitter control (0: none --> higher number: more jitter)
);
in_ApbBus
#(.APB_DW (DataWidth)
, .APB_AW (AddrWidth)
) apbBus ();
ApbDriver
#(.APB_AW (AddrWidth )
, .APB_DW (DataWidth )
, .APB_SW (StrbWidth )
) u_apbDriver
( .ckApb (apbBus.ckApb )
, .apbPRData (apbBus.apbPRData )
, .apbPReady (apbBus.apbPReady )
, .apbPSlvErr (apbBus.apbPSlvErr)
, .apbPSel (apbBus.apbPSel )
, .apbPEnable (apbBus.apbPEnable)
, .apbPAddr (apbBus.apbPAddr )
, .apbPWrite (apbBus.apbPWrite )
, .apbPWData (apbBus.apbPWData )
, .apbPStrb (apbBus.apbPStrb )
, .apbPProt (apbBus.apbPProt )
);
endmodule
/* verilator lint_on UNUSED */
`resetall

58
generateClock.sv Normal file
View file

@ -0,0 +1,58 @@
// V_erilator clock generation module, allows for the clock to be "stepped down" for use within the testbench
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
module generateClock
( output var logic o_clk // Generated clock for testbench
, input var logic i_rootClk // V_erilator clock input
, input var logic [63:0] i_periodHi // Number of rootClk cycles-1 to stay high
, input var logic [63:0] i_periodLo // Number of rootClk cycles-1 to stay low
, input var logic [ 7:0] i_jitterControl // Random jitter control (0: none --> higher number: more jitter)
);
logic intClk_d;
logic intClk_q;
logic [63:0] downCounter_d;
logic [63:0] downCounter_q;
/* svlint off legacy_always */
always @(posedge i_rootClk)
intClk_q <= intClk_d;
always @(posedge i_rootClk)
downCounter_q <= downCounter_d;
/* svlint on legacy_always */
logic [7:0] rndJitter;
always_ff @(posedge i_rootClk)
/* verilator lint_off WIDTH */
rndJitter <= $random;
/* verilator lint_on WIDTH */
logic jitterThisCycle;
assign jitterThisCycle = (rndJitter < i_jitterControl);
always_comb
if (downCounter_q == '0)
if (jitterThisCycle)
downCounter_d = downCounter_q;
else if (intClk_q)
downCounter_d = i_periodLo;
else
downCounter_d = i_periodHi;
else
downCounter_d = downCounter_q - 'd1;
always_comb
if ((downCounter_q == '0) && !jitterThisCycle)
intClk_d = ~intClk_q;
else
intClk_d = intClk_q;
assign o_clk = intClk_q;
endmodule
`resetall

32
in_ApbBus.sv Normal file
View file

@ -0,0 +1,32 @@
// Interface for APB, no modports were used
// SPDX-FileCopyrightText: © 2022 Aadi Desai <21363892+supleed2@users.noreply.github.com>
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/* verilator lint_off UNUSED */
interface in_ApbBus;
event transactionReady; //
event transactionComplete; //
parameter int unsigned APB_AW = 32; // APB Address Width
parameter int unsigned APB_DW = 32; // APB Data Width
parameter int unsigned APB_SW = APB_DW/8; // APB Write Strobe Width
parameter int unsigned APB_AUSER = 0; // Address User Width, set to 0 when unused
localparam int unsigned APB_AU_BITS = (APB_AUSER == 0) ? 1 : APB_AUSER; // Number of bits in address user (auto-computed, do not override)
logic arstApb_n; //
logic ckApb; //
logic [APB_AW-1:0] apbPAddr; //
logic [2:0] apbPProt; //
logic apbPSel; //
logic apbPEnable; //
logic apbPWrite; //
logic [APB_DW-1:0] apbPWData; //
logic [APB_SW-1:0] apbPStrb; //
logic [APB_AU_BITS-1:0] apbPAUser; //
logic [APB_DW-1:0] apbPRData; //
logic apbPSlvErr; //
logic apbPReady; //
endinterface
/* verilator lint_on UNUSED */
`resetall

7
run.sh Normal file
View file

@ -0,0 +1,7 @@
#!/usr/bin/env bash
rm output/*
mkdir -p output
verilator --trace-fst -DUSE_FST -CFLAGS -DUSEFST --cc --exe --default-language 1800-2017 --trace-depth 5 -DN_CYCLES=25 -CFLAGS -DN_CYCLES=25 --Mdir output -Wall apbTest.cpp apbTest.sv
make -C output -f VapbTest.mk VapbTest
time output/VapbTest > output/verilator.log
! grep -q ERROR output/verilator.log