mirror of
https://github.com/supleed2/ELEC70056-HSV-CW2.git
synced 2024-11-10 02:15:47 +00:00
85 lines
3.6 KiB
Systemverilog
85 lines
3.6 KiB
Systemverilog
`timescale 1ns / 1ps
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
//END USER LICENCE AGREEMENT //
|
|
// //
|
|
//Copyright (c) 2012, ARM All rights reserved. //
|
|
// //
|
|
//THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN //
|
|
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
|
|
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
|
|
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
|
|
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
|
|
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
|
|
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
|
|
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
|
|
// //
|
|
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
|
|
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
|
|
//redistribute and use in source and binary forms, with or without modification,//
|
|
//for academic purposes provided the following conditions are met: //
|
|
//a) Redistributions of source code must retain the above copyright notice, this//
|
|
//list of conditions and the following disclaimer. //
|
|
//b) Redistributions in binary form must reproduce the above copyright notice, //
|
|
//this list of conditions and the following disclaimer in the documentation //
|
|
//and/or other materials provided with the distribution. //
|
|
// //
|
|
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
|
|
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
|
|
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
|
|
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
|
|
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
|
|
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
|
|
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
|
|
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
|
|
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
|
|
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
|
|
//////////////////////////////////////////////////////////////////////////////////
|
|
|
|
module GenericCounter(
|
|
CLK,
|
|
RESET,
|
|
ENABLE_IN,
|
|
TRIG_OUT,
|
|
COUNT
|
|
);
|
|
parameter COUNTER_WIDTH=4;
|
|
parameter COUNTER_MAX=4;
|
|
|
|
input CLK;
|
|
input RESET;
|
|
input ENABLE_IN;
|
|
output TRIG_OUT;
|
|
output [COUNTER_WIDTH-1:0] COUNT;
|
|
|
|
reg [COUNTER_WIDTH-1:0] counter;
|
|
reg triggerout;
|
|
|
|
|
|
always@(posedge CLK)begin
|
|
if (RESET)
|
|
counter<=0;
|
|
else begin
|
|
if (ENABLE_IN) begin
|
|
if (counter==(COUNTER_MAX))
|
|
counter<=0;
|
|
else
|
|
counter<=counter+1;
|
|
end
|
|
end
|
|
end
|
|
|
|
always@(posedge CLK)begin
|
|
if (RESET)
|
|
triggerout<=0;
|
|
else begin
|
|
if (ENABLE_IN && (counter==(COUNTER_MAX)))
|
|
triggerout<=1;
|
|
else
|
|
triggerout<=0;
|
|
end
|
|
end
|
|
|
|
assign COUNT=counter;
|
|
assign TRIG_OUT=triggerout;
|
|
|
|
endmodule |