ELEC70056-HSV-CW2/rtl/AHB_VGA/vga_image.sv

90 lines
3.9 KiB
Systemverilog

//////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT //
// //
//Copyright (c) 2012, ARM All rights reserved. //
// //
//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
//////////////////////////////////////////////////////////////////////////////////
module vga_image(
input wire clk,
input wire resetn,
input wire [9:0] pixel_x,
input wire [9:0] pixel_y,
input wire image_we,
input wire [7:0] image_data,
input wire [15:0] address,
output wire [7:0] image_rgb
);
wire [15:0] addr_r;
wire [14:0] addr_w;
wire [7:0] din;
wire [7:0] dout;
wire [9:0] img_x;
wire [9:0] img_y;
reg [15:0] address_reg;
//buffer address = bus address -1 , as the first address is used for console
always @(posedge clk)
address_reg <= address-1;
//Frame buffer
dual_port_ram_sync
#(.ADDR_WIDTH(15), .DATA_WIDTH(8))
uimage_ram
( .clk(clk),
.we(image_we),
.addr_a(addr_w),
.addr_b(addr_r),
.din_a(din),
.dout_a(),
.dout_b(dout)
);
assign addr_w = address_reg[14:0];
assign din = image_data;
assign img_x = pixel_x[9:0]-240;
assign img_y = pixel_y[9:0];
assign addr_r = {1'b0,img_y[8:2], img_x[8:2]};
assign image_rgb = dout;
endmodule