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https://github.com/supleed2/ELEC70056-HSV-CW2.git
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136 lines
5 KiB
Systemverilog
136 lines
5 KiB
Systemverilog
//////////////////////////////////////////////////////////////////////////////////
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//END USER LICENCE AGREEMENT //
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// //
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//Copyright (c) 2012, ARM All rights reserved. //
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// //
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//THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN //
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//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
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//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
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//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
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//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
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//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
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//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
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//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
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// //
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//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
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//a non-exclusive, worldwide, non-transferable, copyright licence only to //
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//redistribute and use in source and binary forms, with or without modification,//
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//for academic purposes provided the following conditions are met: //
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//a) Redistributions of source code must retain the above copyright notice, this//
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//list of conditions and the following disclaimer. //
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//b) Redistributions in binary form must reproduce the above copyright notice, //
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//this list of conditions and the following disclaimer in the documentation //
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//and/or other materials provided with the distribution. //
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// //
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//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
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//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
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//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
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//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
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//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
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//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
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//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
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//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
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//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
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// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
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//////////////////////////////////////////////////////////////////////////////////
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module VGAInterface(
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input CLK,
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input resetn,
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input [7:0] COLOUR_IN,
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output reg [7:0] cout,
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output reg hs,
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output reg vs,
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output reg [9:0] addrh,
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output reg [9:0] addrv
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);
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// Time in Vertical Lines
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parameter VertTimeToPulseWidthEnd = 10'd2;
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parameter VertTimeToBackPorchEnd = 10'd31;
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parameter VertTimeToDisplayTimeEnd = 10'd511;
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parameter VertTimeToFrontPorchEnd = 10'd521;
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// Time in Horizontal Lines
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parameter HorzTimeToPulseWidthEnd = 10'd96;
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parameter HorzTimeToBackPorchEnd = 10'd144;
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parameter HorzTimeToDisplayTimeEnd = 10'd784;
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parameter HorzTimeToFrontPorchEnd = 10'd800;
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wire TrigHOut, TrigDiv;
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wire [9:0] HorzCount;
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wire [9:0] VertCount;
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wire reset = ~resetn;
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//Divide the clock frequency
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GenericCounter #(.COUNTER_WIDTH(1), .COUNTER_MAX(1))
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FreqDivider
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(
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.CLK(CLK),
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.RESET(reset),
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.ENABLE_IN(1'b1),
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.TRIG_OUT(TrigDiv)
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);
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//Horizontal counter
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GenericCounter #(.COUNTER_WIDTH(10), .COUNTER_MAX(HorzTimeToFrontPorchEnd))
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HorzAddrCounter
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(
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.CLK(CLK),
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.RESET(reset),
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.ENABLE_IN(TrigDiv),
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.TRIG_OUT(TrigHOut),
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.COUNT(HorzCount)
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);
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//Vertical counter
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GenericCounter #(.COUNTER_WIDTH(10), .COUNTER_MAX(VertTimeToFrontPorchEnd))
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VertAddrCounter
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(
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.CLK(CLK),
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.RESET(reset),
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.ENABLE_IN(TrigHOut),
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.COUNT(VertCount)
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);
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//Synchronisation signals
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always@(posedge CLK) begin
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if(HorzCount<HorzTimeToPulseWidthEnd)
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hs <= 1'b0;
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else
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hs <= 1'b1;
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if(VertCount<VertTimeToPulseWidthEnd)
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vs <= 1'b0;
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else
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vs <= 1'b1;
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end
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//Color signals
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always@(posedge CLK) begin
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if ( ( (HorzCount >= HorzTimeToBackPorchEnd ) && (HorzCount < HorzTimeToDisplayTimeEnd) ) &&
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( (VertCount >= VertTimeToBackPorchEnd ) && (VertCount < VertTimeToDisplayTimeEnd) ) )
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cout <= COLOUR_IN;
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else
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cout <= 8'b00000000;
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end
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//output horizontal and vertical addresses
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always@(posedge CLK)begin
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if ((HorzCount>HorzTimeToBackPorchEnd)&&(HorzCount<HorzTimeToDisplayTimeEnd))
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addrh<=HorzCount-HorzTimeToBackPorchEnd;
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else
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addrh<=10'b0000000000;
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end
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always@(posedge CLK)begin
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if ((VertCount>VertTimeToBackPorchEnd)&&(VertCount<VertTimeToDisplayTimeEnd))
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addrv<=VertCount-VertTimeToBackPorchEnd;
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else
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addrv<=10'b0000000000;
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end
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endmodule
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