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23 lines
514 B
Systemverilog
23 lines
514 B
Systemverilog
module VGACOMPARATOR
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( input logic [31:0] HRDATA1
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, input logic HREADYOUT1
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, input logic HSYNC1
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, input logic VSYNC1
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, input logic [ 7:0] RGB1
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, input logic [31:0] HRDATA2
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, input logic HREADYOUT2
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, input logic HSYNC2
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, input logic VSYNC2
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, input logic [ 7:0] RGB2
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, output logic MISMATCH
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);
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assign MISMATCH =
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!( HRDATA1 == HRDATA2
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&& HREADYOUT1 == HREADYOUT2
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&& HSYNC1 == HSYNC2
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&& VSYNC1 == VSYNC2
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&& RGB1 == RGB2
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)
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endmodule |