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https://github.com/supleed2/ELEC70056-HSV-CW2.git
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342 lines
10 KiB
Systemverilog
342 lines
10 KiB
Systemverilog
//////////////////////////////////////////////////////////////////////////////////
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//END USER LICENCE AGREEMENT //
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// //
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//Copyright (c) 2012, ARM All rights reserved. //
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// //
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//THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN //
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//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
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//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
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//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
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//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
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//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
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//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
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//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
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// //
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//ARM hereby grants to you, subject to the terms and conditions of this Licence,//
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//a non-exclusive, worldwide, non-transferable, copyright licence only to //
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//redistribute and use in source and binary forms, with or without modification,//
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//for academic purposes provided the following conditions are met: //
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//a) Redistributions of source code must retain the above copyright notice, this//
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//list of conditions and the following disclaimer. //
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//b) Redistributions in binary form must reproduce the above copyright notice, //
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//this list of conditions and the following disclaimer in the documentation //
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//and/or other materials provided with the distribution. //
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// //
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//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
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//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
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//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
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//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
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//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
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//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
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//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
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//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
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//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
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// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
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//////////////////////////////////////////////////////////////////////////////////
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module AHBLITE_SYS(
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//CLOCKS & RESET
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input wire CLK,
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input wire RESET,
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//TO BOARD LEDs
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output wire [7:0] LED,
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// Switch Inputs
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input wire [7:0] SW,
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//VGA IO
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output wire [2:0] VGARED,
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output wire [2:0] VGAGREEN,
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output wire [1:0] VGABLUE,
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output wire HSYNC, //VGA Horizontal Sync
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output wire VSYNC, //VGA Vertical Sync
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// Debug
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input wire TCK_SWCLK, // SWD Clk / JTAG TCK
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input wire TDI_NC, // NC / JTAG TDI
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inout wire TMS_SWDIO, // SWD I/O / JTAG TMS
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output wire TDO_SWO // SW Out / JTAG TDO
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);
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//AHB-LITE SIGNALS
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//Global Signals
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wire HCLK;
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wire HRESETn;
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//Address, Control & Write Data Signals
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wire [31:0] HADDR;
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wire [31:0] HWDATA;
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wire HWRITE;
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wire [1:0] HTRANS;
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wire [2:0] HBURST;
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wire HMASTLOCK;
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wire [3:0] HPROT;
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wire [2:0] HSIZE;
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//Transfer Response & Read Data Signals
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wire [31:0] HRDATA;
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wire HRESP;
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wire HREADY;
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//SELECT SIGNALS
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wire [3:0] MUX_SEL;
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wire HSEL_MEM;
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wire HSEL_GPIO;
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wire HSEL_VGA;
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//SLAVE READ DATA
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wire [31:0] HRDATA_MEM;
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wire [31:0] HRDATA_GPIO;
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wire [31:0] HRDATA_VGA;
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//SLAVE HREADYOUT
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wire HREADYOUT_MEM;
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wire HREADYOUT_GPIO;
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wire HREADYOUT_VGA;
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//CM0-DS Sideband signals
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wire [31:0] IRQ;
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// CM-DS Sideband signals
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wire lockup;
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wire lockup_reset_req;
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wire sys_reset_req;
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//SYSTEM GENERATES NO ERROR RESPONSE
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assign HRESP = 1'b0;
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// Interrupt signals
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assign IRQ = 32'h00000000;
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// Clock
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wire fclk; // Free running clock
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// Reset
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wire reset_n = RESET;
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// Clock divider, divide the frequency by two, hence less time constraint
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reg clk_div;
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always @(posedge CLK)
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begin
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clk_div=~clk_div;
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end
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assign fclk = clk_div;
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// Reset synchronizer
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reg [4:0] reset_sync_reg;
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assign lockup_reset_req = 1'b0;
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always @(posedge fclk or negedge reset_n)
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begin
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if (!reset_n)
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reset_sync_reg <= 5'b00000;
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else
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begin
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reset_sync_reg[3:0] <= {reset_sync_reg[2:0], 1'b1};
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reset_sync_reg[4] <= reset_sync_reg[2] &
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(~(sys_reset_req | (lockup & lockup_reset_req)));
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end
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end
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// CPU System Bus
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assign HCLK = fclk;
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assign HRESETn = reset_sync_reg[4];
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// Debug signals (DesignStart Cortex-M0 supports only SWD)
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wire dbg_swdo_en;
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wire dbg_swdo;
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wire dbg_swdi;
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assign TMS_SWDIO = dbg_swdo_en ? dbg_swdo : 1'bz;
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assign dbg_swdi = TMS_SWDIO;
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wire cdbgpwrupreq2ack;
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// DesignStart simplified integration level
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CORTEXM0INTEGRATION u_CORTEXM0INTEGRATION (
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// CLOCK AND RESETS
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.FCLK (fclk),
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.SCLK (fclk),
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.HCLK (fclk),
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.DCLK (fclk),
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.PORESETn (reset_sync_reg[2]),
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.DBGRESETn (reset_sync_reg[3]),
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.HRESETn (HRESETn),
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.SWCLKTCK (TCK_SWCLK),
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.nTRST (1'b1),
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// AHB-LITE MASTER PORT
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.HADDR (HADDR),
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.HBURST (HBURST),
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.HMASTLOCK (HMASTLOCK),
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.HPROT (HPROT),
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.HSIZE (HSIZE),
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.HTRANS (HTRANS),
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.HWDATA (HWDATA),
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.HWRITE (HWRITE),
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.HRDATA (HRDATA),
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.HREADY (HREADY),
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.HRESP (HRESP),
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.HMASTER (),
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// CODE SEQUENTIALITY AND SPECULATION
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.CODENSEQ (),
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.CODEHINTDE (),
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.SPECHTRANS (),
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// DEBUG
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.SWDITMS (dbg_swdi),
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.TDI (TDI_NS),
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.SWDO (dbg_swdo),
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.SWDOEN (dbg_swdo_en),
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.TDO (TDO_SWO),
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.nTDOEN (),
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.DBGRESTART (1'b0),
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.DBGRESTARTED (),
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.EDBGRQ (1'b0), // External Debug request to CPU
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.HALTED (),
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// MISC
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.NMI (1'b0), // Non-maskable interrupt input
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.IRQ (IRQ), // Interrupt request inputs
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.TXEV (), // Event output (SEV executed)
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.RXEV (1'b0), // Event input
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.LOCKUP (lockup), // Core is locked-up
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.SYSRESETREQ (sys_reset_req), // System reset request
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.STCALIB ({1'b1, // No alternative clock source
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1'b0, // Exact multiple of 10ms from FCLK
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24'h007A11F}), // Calibration value for SysTick for 50 MHz source
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.STCLKEN (1'b0), // SysTick SCLK clock disable
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.IRQLATENCY (8'h00),
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.ECOREVNUM (28'h0),
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// POWER MANAGEMENT
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.GATEHCLK (),
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.SLEEPING (), // Core and NVIC sleeping
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.SLEEPDEEP (),
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.WAKEUP (),
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.WICSENSE (),
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.SLEEPHOLDREQn (1'b1),
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.SLEEPHOLDACKn (),
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.WICENREQ (1'b0),
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.WICENACK (),
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.CDBGPWRUPREQ (cdbgpwrupreq2ack),
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.CDBGPWRUPACK (cdbgpwrupreq2ack),
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// SCAN IO
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.SE (1'b0),
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.RSTBYPASS (1'b0)
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);
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//Address Decoder
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AHBDCD uAHBDCD (
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.HADDR(HADDR[31:0]),
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.HSEL_S0(HSEL_MEM),
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.HSEL_S1(HSEL_VGA),
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.HSEL_S2(),
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.HSEL_S3(),
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.HSEL_S4(HSEL_GPIO),
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.HSEL_S5(),
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.HSEL_S6(),
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.HSEL_S7(),
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.HSEL_S8(),
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.HSEL_S9(),
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.HSEL_NOMAP(),
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.MUX_SEL(MUX_SEL[3:0])
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);
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//Slave to Master Mulitplexor
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AHBMUX uAHBMUX (
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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.MUX_SEL(MUX_SEL[3:0]),
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.HRDATA_S0(HRDATA_MEM),
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.HRDATA_S1(HRDATA_VGA),
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.HRDATA_S2(32'h00000000),
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.HRDATA_S3(32'h00000000),
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.HRDATA_S4(HRDATA_GPIO),
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.HRDATA_S5(32'h00000000),
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.HRDATA_S6(32'h00000000),
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.HRDATA_S7(32'h00000000),
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.HRDATA_S8(32'h00000000),
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.HRDATA_S9(32'h00000000),
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.HRDATA_NOMAP(32'hDEADBEEF),
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.HREADYOUT_S0(HREADYOUT_MEM),
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.HREADYOUT_S1(HREADYOUT_VGA),
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.HREADYOUT_S2(1'b1),
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.HREADYOUT_S3(1'b1),
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.HREADYOUT_S4(HREADYOUT_GPIO),
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.HREADYOUT_S5(1'b1),
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.HREADYOUT_S6(1'b1),
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.HREADYOUT_S7(1'b1),
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.HREADYOUT_S8(1'b1),
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.HREADYOUT_S9(1'b1),
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.HREADYOUT_NOMAP(1'b1),
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.HRDATA(HRDATA[31:0]),
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.HREADY(HREADY)
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);
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// AHBLite Peripherals
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// AHB-Lite RAM
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AHB2MEM uAHB2MEM (
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//AHBLITE Signals
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.HSEL(HSEL_MEM),
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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.HREADY(HREADY),
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.HADDR(HADDR),
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.HTRANS(HTRANS[1:0]),
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.HWRITE(HWRITE),
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.HSIZE(HSIZE),
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.HWDATA(HWDATA[31:0]),
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.HRDATA(HRDATA_MEM),
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.HREADYOUT(HREADYOUT_MEM)
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);
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// AHBLite VGA Peripheral
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AHBVGA uAHBVGA (
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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.HADDR(HADDR),
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.HWDATA(HWDATA),
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.HREADY(HREADY),
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.HWRITE(HWRITE),
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.HTRANS(HTRANS),
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.HSEL(HSEL_VGA),
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.HRDATA(HRDATA_VGA),
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.HREADYOUT(HREADYOUT_VGA),
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.HSYNC(HSYNC),
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.VSYNC(VSYNC),
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.RGB({VGARED,VGAGREEN,VGABLUE})
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);
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// AHBLite GPIO
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AHBGPIO uAHBGPIO(
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.HCLK(HCLK),
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.HRESETn(HRESETn),
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.HADDR(HADDR),
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.HWDATA(HWDATA),
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.HREADY(HREADY),
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.HWRITE(HWRITE),
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.HTRANS(HTRANS),
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.HSEL(HSEL_GPIO),
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.HRDATA(HRDATA_GPIO),
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.HREADYOUT(HREADYOUT_GPIO),
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.GPIOIN({8'b00000000,SW[7:0]}),
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.GPIOOUT(LED[7:0])
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);
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endmodule
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