mirror of
https://github.com/supleed2/ELEC70056-HSV-CW2.git
synced 2024-09-19 20:56:18 +00:00
113 lines
3.3 KiB
Systemverilog
113 lines
3.3 KiB
Systemverilog
// --========================================================================--
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// Version and Release Control Information:
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//
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// File Name : AHB2BRAM.v
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// File Revision : 1.60
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//
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// ----------------------------------------------------------------------------
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// Purpose : Basic AHBLITE Internal Memory Default Size = 16KB
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//
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// --========================================================================--
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module AHB2MEM
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#(parameter MEMWIDTH = 14) // SIZE[Bytes] = 2 ^ MEMWIDTH[Bytes] = 2 ^ MEMWIDTH / 4[Entries]
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(
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//AHBLITE INTERFACE
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//Slave Select Signals
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input wire HSEL,
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//Global Signal
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input wire HCLK,
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input wire HRESETn,
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//Address, Control & Write Data
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input wire HREADY,
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input wire [31:0] HADDR,
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input wire [1:0] HTRANS,
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input wire HWRITE,
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input wire [2:0] HSIZE,
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input wire [31:0] HWDATA,
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// Transfer Response & Read Data
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output wire HREADYOUT,
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output reg [31:0] HRDATA
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);
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assign HREADYOUT = 1'b1; // Always ready
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// Memory Array
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reg [31:0] memory[0:(2**(MEMWIDTH-2)-1)];
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initial
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begin
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$readmemh("code.hex", memory);
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end
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// Registers to store Adress Phase Signals
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reg APhase_HSEL;
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reg APhase_HWRITE;
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reg [1:0] APhase_HTRANS;
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reg [31:0] APhase_HRADDR;
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reg [31:0] APhase_HWADDR;
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reg [2:0] APhase_HSIZE;
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// Sample the Address Phase
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always @(posedge HCLK or negedge HRESETn)
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begin
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if(!HRESETn)
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begin
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APhase_HSEL <= 1'b0;
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APhase_HWRITE <= 1'b0;
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APhase_HTRANS <= 2'b00;
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APhase_HWADDR <= 32'h0;
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APhase_HSIZE <= 3'b000;
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APhase_HRADDR[MEMWIDTH-2:0] <= {(MEMWIDTH-1){1'b0}};
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end
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else if(HREADY)
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begin
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APhase_HSEL <= HSEL;
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APhase_HWRITE <= HWRITE;
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APhase_HTRANS <= HTRANS;
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APhase_HWADDR <= HADDR;
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APhase_HSIZE <= HSIZE;
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APhase_HRADDR[MEMWIDTH-2:0] <= HADDR[MEMWIDTH:2];
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end
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end
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// Decode the bytes lanes depending on HSIZE & HADDR[1:0]
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wire tx_byte = ~APhase_HSIZE[1] & ~APhase_HSIZE[0];
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wire tx_half = ~APhase_HSIZE[1] & APhase_HSIZE[0];
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wire tx_word = APhase_HSIZE[1];
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wire byte_at_00 = tx_byte & ~APhase_HWADDR[1] & ~APhase_HWADDR[0];
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wire byte_at_01 = tx_byte & ~APhase_HWADDR[1] & APhase_HWADDR[0];
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wire byte_at_10 = tx_byte & APhase_HWADDR[1] & ~APhase_HWADDR[0];
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wire byte_at_11 = tx_byte & APhase_HWADDR[1] & APhase_HWADDR[0];
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wire half_at_00 = tx_half & ~APhase_HWADDR[1];
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wire half_at_10 = tx_half & APhase_HWADDR[1];
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wire word_at_00 = tx_word;
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wire byte0 = word_at_00 | half_at_00 | byte_at_00;
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wire byte1 = word_at_00 | half_at_00 | byte_at_01;
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wire byte2 = word_at_00 | half_at_10 | byte_at_10;
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wire byte3 = word_at_00 | half_at_10 | byte_at_11;
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always @ (posedge HCLK)
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begin
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if(APhase_HSEL & APhase_HWRITE & APhase_HTRANS[1])
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begin
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if(byte0)
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memory[APhase_HWADDR[MEMWIDTH:2]][ 7: 0] <= HWDATA[ 7: 0];
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if(byte1)
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memory[APhase_HWADDR[MEMWIDTH:2]][15: 8] <= HWDATA[15: 8];
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if(byte2)
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memory[APhase_HWADDR[MEMWIDTH:2]][23:16] <= HWDATA[23:16];
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if(byte3)
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memory[APhase_HWADDR[MEMWIDTH:2]][31:24] <= HWDATA[31:24];
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end
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HRDATA = memory[HADDR[MEMWIDTH:2]];
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end
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endmodule
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