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Add redundant VGA and comparator module

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This commit is contained in:
Alden0012 2022-11-08 17:49:23 +00:00
parent 4edfce0e03
commit f50d0c5c2e
2 changed files with 116 additions and 52 deletions
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145
rtl/AHBLITE_SYS.sv
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@ -38,30 +38,31 @@
module AHBLITE_SYS( module AHBLITE_SYS(
//CLOCKS & RESET //CLOCKS & RESET
input wire CLK, input wire CLK,
input wire RESET, input wire RESET,
//TO BOARD LEDs //TO BOARD LEDs
output wire [7:0] LED, output wire [7:0] LED,
// Switch Inputs // Switch Inputs
input wire [7:0] SW, input wire [7:0] SW,
//VGA IO //VGA IO
output wire [2:0] VGARED, output wire [2:0] VGARED,
output wire [2:0] VGAGREEN, output wire [2:0] VGAGREEN,
output wire [1:0] VGABLUE, output wire [1:0] VGABLUE,
output wire HSYNC, //VGA Horizontal Sync output wire HSYNC, //VGA Horizontal Sync
output wire VSYNC, //VGA Vertical Sync output wire VSYNC, //VGA Vertical Sync
// Debug // Debug
input wire TCK_SWCLK, // SWD Clk / JTAG TCK input wire TCK_SWCLK, // SWD Clk / JTAG TCK
input wire TDI_NC, // NC / JTAG TDI input wire TDI_NC, // NC / JTAG TDI
inout wire TMS_SWDIO, // SWD I/O / JTAG TMS inout wire TMS_SWDIO, // SWD I/O / JTAG TMS
output wire TDO_SWO // SW Out / JTAG TDO output wire TDO_SWO, // SW Out / JTAG TDO
output wire VGA_MISMATCH
); );
//AHB-LITE SIGNALS //AHB-LITE SIGNALS
//Global Signals //Global Signals
wire HCLK; wire HCLK;
wire HRESETn; wire HRESETn;
@ -82,19 +83,19 @@ wire HREADY;
//SELECT SIGNALS //SELECT SIGNALS
wire [3:0] MUX_SEL; wire [3:0] MUX_SEL;
wire HSEL_MEM; wire HSEL_MEM;
wire HSEL_GPIO; wire HSEL_GPIO;
wire HSEL_VGA; wire HSEL_VGA;
//SLAVE READ DATA //SLAVE READ DATA
wire [31:0] HRDATA_MEM; wire [31:0] HRDATA_MEM;
wire [31:0] HRDATA_GPIO; wire [31:0] HRDATA_GPIO;
wire [31:0] HRDATA_VGA; wire [31:0] HRDATA_VGA;
//SLAVE HREADYOUT //SLAVE HREADYOUT
wire HREADYOUT_MEM; wire HREADYOUT_MEM;
wire HREADYOUT_GPIO; wire HREADYOUT_GPIO;
wire HREADYOUT_VGA; wire HREADYOUT_VGA;
//CM0-DS Sideband signals //CM0-DS Sideband signals
wire [31:0] IRQ; wire [31:0] IRQ;
@ -104,6 +105,15 @@ wire lockup;
wire lockup_reset_req; wire lockup_reset_req;
wire sys_reset_req; wire sys_reset_req;
// VGA Redundant Signals
wire [31:0] HRDATA_VGA_2;
wire HREADYOUT_VGA_2;
wire HSYNC_2;
wire VSYNC_2;
wire [2:0] VGARED_2,
wire [2:0] VGAGREEN_2,
wire [1:0] VGABLUE_2,
//SYSTEM GENERATES NO ERROR RESPONSE //SYSTEM GENERATES NO ERROR RESPONSE
assign HRESP = 1'b0; assign HRESP = 1'b0;
@ -115,14 +125,14 @@ wire fclk; // Free running clock
// Reset // Reset
wire reset_n = RESET; wire reset_n = RESET;
// Clock divider, divide the frequency by two, hence less time constraint // Clock divider, divide the frequency by two, hence less time constraint
reg clk_div; reg clk_div;
always @(posedge CLK) always @(posedge CLK)
begin begin
clk_div=~clk_div; clk_div=~clk_div;
end end
assign fclk = clk_div; assign fclk = clk_div;
// Reset synchronizer // Reset synchronizer
reg [4:0] reset_sync_reg; reg [4:0] reset_sync_reg;
@ -228,11 +238,11 @@ CORTEXM0INTEGRATION u_CORTEXM0INTEGRATION (
.RSTBYPASS (1'b0) .RSTBYPASS (1'b0)
); );
//Address Decoder //Address Decoder
AHBDCD uAHBDCD ( AHBDCD uAHBDCD (
.HADDR(HADDR[31:0]), .HADDR(HADDR[31:0]),
.HSEL_S0(HSEL_MEM), .HSEL_S0(HSEL_MEM),
.HSEL_S1(HSEL_VGA), .HSEL_S1(HSEL_VGA),
.HSEL_S2(), .HSEL_S2(),
@ -244,7 +254,7 @@ AHBDCD uAHBDCD (
.HSEL_S8(), .HSEL_S8(),
.HSEL_S9(), .HSEL_S9(),
.HSEL_NOMAP(), .HSEL_NOMAP(),
.MUX_SEL(MUX_SEL[3:0]) .MUX_SEL(MUX_SEL[3:0])
); );
@ -254,7 +264,7 @@ AHBMUX uAHBMUX (
.HCLK(HCLK), .HCLK(HCLK),
.HRESETn(HRESETn), .HRESETn(HRESETn),
.MUX_SEL(MUX_SEL[3:0]), .MUX_SEL(MUX_SEL[3:0]),
.HRDATA_S0(HRDATA_MEM), .HRDATA_S0(HRDATA_MEM),
.HRDATA_S1(HRDATA_VGA), .HRDATA_S1(HRDATA_VGA),
.HRDATA_S2(32'h00000000), .HRDATA_S2(32'h00000000),
@ -266,7 +276,7 @@ AHBMUX uAHBMUX (
.HRDATA_S8(32'h00000000), .HRDATA_S8(32'h00000000),
.HRDATA_S9(32'h00000000), .HRDATA_S9(32'h00000000),
.HRDATA_NOMAP(32'hDEADBEEF), .HRDATA_NOMAP(32'hDEADBEEF),
.HREADYOUT_S0(HREADYOUT_MEM), .HREADYOUT_S0(HREADYOUT_MEM),
.HREADYOUT_S1(HREADYOUT_VGA), .HREADYOUT_S1(HREADYOUT_VGA),
.HREADYOUT_S2(1'b1), .HREADYOUT_S2(1'b1),
@ -278,7 +288,7 @@ AHBMUX uAHBMUX (
.HREADYOUT_S8(1'b1), .HREADYOUT_S8(1'b1),
.HREADYOUT_S9(1'b1), .HREADYOUT_S9(1'b1),
.HREADYOUT_NOMAP(1'b1), .HREADYOUT_NOMAP(1'b1),
.HRDATA(HRDATA[31:0]), .HRDATA(HRDATA[31:0]),
.HREADY(HREADY) .HREADY(HREADY)
); );
@ -290,37 +300,68 @@ AHBMUX uAHBMUX (
AHB2MEM uAHB2MEM ( AHB2MEM uAHB2MEM (
//AHBLITE Signals //AHBLITE Signals
.HSEL(HSEL_MEM), .HSEL(HSEL_MEM),
.HCLK(HCLK), .HCLK(HCLK),
.HRESETn(HRESETn), .HRESETn(HRESETn),
.HREADY(HREADY), .HREADY(HREADY),
.HADDR(HADDR), .HADDR(HADDR),
.HTRANS(HTRANS[1:0]), .HTRANS(HTRANS[1:0]),
.HWRITE(HWRITE), .HWRITE(HWRITE),
.HSIZE(HSIZE), .HSIZE(HSIZE),
.HWDATA(HWDATA[31:0]), .HWDATA(HWDATA[31:0]),
.HRDATA(HRDATA_MEM), .HRDATA(HRDATA_MEM),
.HREADYOUT(HREADYOUT_MEM) .HREADYOUT(HREADYOUT_MEM)
); );
// AHBLite VGA Peripheral // AHBLite VGA Peripheral
AHBVGA uAHBVGA ( AHBVGA uAHBVGA (
.HCLK(HCLK), .HCLK(HCLK),
.HRESETn(HRESETn), .HRESETn(HRESETn),
.HADDR(HADDR), .HADDR(HADDR),
.HWDATA(HWDATA), .HWDATA(HWDATA),
.HREADY(HREADY), .HREADY(HREADY),
.HWRITE(HWRITE), .HWRITE(HWRITE),
.HTRANS(HTRANS), .HTRANS(HTRANS),
.HSEL(HSEL_VGA), .HSEL(HSEL_VGA),
.HRDATA(HRDATA_VGA), .HRDATA(HRDATA_VGA),
.HREADYOUT(HREADYOUT_VGA), .HREADYOUT(HREADYOUT_VGA),
.HSYNC(HSYNC), .HSYNC(HSYNC),
.VSYNC(VSYNC), .VSYNC(VSYNC),
.RGB({VGARED,VGAGREEN,VGABLUE}) .RGB({VGARED,VGAGREEN,VGABLUE})
); );
// AHBLite GPIO // AHBLite VGA Peripheral (Redundant)
AHBVGA uAHBVGA2 (
.HCLK(HCLK),
.HRESETn(HRESETn),
.HADDR(HADDR),
.HWDATA(HWDATA),
.HREADY(HREADY),
.HWRITE(HWRITE),
.HTRANS(HTRANS),
.HSEL(HSEL_VGA),
.HRDATA(HRDATA_VGA_2),
.HREADYOUT(HREADYOUT_VGA_2),
.HSYNC(HSYNC_2),
.VSYNC(VSYNC_2),
.RGB({VGARED_2,VGAGREEN_2,VGABLUE_2})
);
VGACOMPARATOR uVGACOMPARATOR (
.HRDATA1 (HRDATA_VGA),
.HREADYOUT1 (HREADYOUT_VGA),
.HSYNC1 (HSYNC),
.VSYNC1 (VSYNC),
.RGB1 ({VGARED,VGAGREEN,VGABLUE}),
.HRDATA2 (HRDATA_VGA_2),
.HREADYOUT2 (HREADYOUT_VGA_2),
.HSYNC2 (HSYNC_2),
.VSYNC2 (VSYNC_2),
.RGB2 ({VGARED_2,VGAGREEN_2,VGABLUE_2}),
.MISMATCH (VGA_MISMATCH)
);
// AHBLite GPIO
AHBGPIO uAHBGPIO( AHBGPIO uAHBGPIO(
.HCLK(HCLK), .HCLK(HCLK),
.HRESETn(HRESETn), .HRESETn(HRESETn),
@ -333,9 +374,9 @@ AHBGPIO uAHBGPIO(
.HSEL(HSEL_GPIO), .HSEL(HSEL_GPIO),
.HRDATA(HRDATA_GPIO), .HRDATA(HRDATA_GPIO),
.HREADYOUT(HREADYOUT_GPIO), .HREADYOUT(HREADYOUT_GPIO),
.GPIOIN({8'b00000000,SW[7:0]}), .GPIOIN({8'b00000000,SW[7:0]}),
.GPIOOUT(LED[7:0]) .GPIOOUT(LED[7:0])
); );
endmodule endmodule

23
rtl/AHB_VGA/VGACOMPARATOR.sv Normal file
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@ -0,0 +1,23 @@
module VGACOMPARATOR
( input logic [31:0] HRDATA1
, input logic HREADYOUT1
, input logic HSYNC1
, input logic VSYNC1
, input logic [ 7:0] RGB1
, input logic [31:0] HRDATA2
, input logic HREADYOUT2
, input logic HSYNC2
, input logic VSYNC2
, input logic [ 7:0] RGB2
, output logic MISMATCH
);
assign MISMATCH =
!( HRDATA1 == HRDATA2
&& HREADYOUT1 == HREADYOUT2
&& HSYNC1 == HSYNC2
&& VSYNC1 == VSYNC2
&& RGB1 == RGB2
)
endmodule