Add redundant VGA and comparator module

rtl/AHBLITE_SYS.sv

@@ -58,7 +58,8 @@ module AHBLITE_SYS(
     	input   wire            TCK_SWCLK,               // SWD Clk / JTAG TCK
     	input   wire            TDI_NC,                  // NC      / JTAG TDI
     	inout   wire            TMS_SWDIO,               // SWD I/O / JTAG TMS
-    	output  wire            TDO_SWO                  // SW  Out / JTAG TDO
+    	output  wire            TDO_SWO,                 // SW  Out / JTAG TDO
+        output  wire            VGA_MISMATCH
 );
 
 //AHB-LITE SIGNALS
@@ -104,6 +105,15 @@ wire            	lockup;
 wire            	lockup_reset_req;
 wire            	sys_reset_req;
 
+// VGA Redundant Signals
+wire [31:0] 		HRDATA_VGA_2;
+wire 			    HREADYOUT_VGA_2;
+wire                HSYNC_2;
+wire                VSYNC_2;
+wire [2:0]          VGARED_2,
+wire [2:0]          VGAGREEN_2,
+wire [1:0]          VGABLUE_2,
+
 //SYSTEM GENERATES NO ERROR RESPONSE
 assign 			HRESP = 1'b0;
 
@@ -320,6 +330,37 @@ AHBVGA uAHBVGA (
     .RGB({VGARED,VGAGREEN,VGABLUE})
     );
 
+// AHBLite VGA Peripheral (Redundant)
+AHBVGA uAHBVGA2 (
+    .HCLK(HCLK),
+    .HRESETn(HRESETn),
+    .HADDR(HADDR),
+    .HWDATA(HWDATA),
+    .HREADY(HREADY),
+    .HWRITE(HWRITE),
+    .HTRANS(HTRANS),
+    .HSEL(HSEL_VGA),
+    .HRDATA(HRDATA_VGA_2),
+    .HREADYOUT(HREADYOUT_VGA_2),
+    .HSYNC(HSYNC_2),
+    .VSYNC(VSYNC_2),
+    .RGB({VGARED_2,VGAGREEN_2,VGABLUE_2})
+    );
+
+VGACOMPARATOR uVGACOMPARATOR (
+    .HRDATA1    (HRDATA_VGA),
+    .HREADYOUT1 (HREADYOUT_VGA),
+    .HSYNC1     (HSYNC),
+    .VSYNC1     (VSYNC),
+    .RGB1       ({VGARED,VGAGREEN,VGABLUE}),
+    .HRDATA2    (HRDATA_VGA_2),
+    .HREADYOUT2 (HREADYOUT_VGA_2),
+    .HSYNC2     (HSYNC_2),
+    .VSYNC2     (VSYNC_2),
+    .RGB2       ({VGARED_2,VGAGREEN_2,VGABLUE_2}),
+    .MISMATCH   (VGA_MISMATCH)
+);
+
 // AHBLite GPIO
 AHBGPIO uAHBGPIO(
 	.HCLK(HCLK),

rtl/AHB_VGA/VGACOMPARATOR.sv

@@ -0,0 +1,23 @@
+module VGACOMPARATOR
+( input  logic [31:0] HRDATA1
+, input  logic        HREADYOUT1
+, input  logic        HSYNC1
+, input  logic        VSYNC1
+, input  logic [ 7:0] RGB1
+, input  logic [31:0] HRDATA2
+, input  logic        HREADYOUT2
+, input  logic        HSYNC2
+, input  logic        VSYNC2
+, input  logic [ 7:0] RGB2
+, output logic        MISMATCH
+);
+
+  assign MISMATCH =
+    !( HRDATA1 == HRDATA2
+    && HREADYOUT1 == HREADYOUT2
+    && HSYNC1 == HSYNC2
+    && VSYNC1 == VSYNC2
+    && RGB1 == RGB2
+    )
+
+endmodule