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https://github.com/supleed2/ELEC70056-HSV-CW2.git
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Add initial GPIO test-bench
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172
tbench/ahb_gpio_tb.sv
Normal file
172
tbench/ahb_gpio_tb.sv
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//stub
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interface ahb_gpio_if;
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typedef enum bit[1:0] {
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IDLE = 2'b00,
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BUSY = 2'b01,
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NONSEQUENTIAL = 2'b10,
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SEQUENTIAL = 2'b11
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} htrans_types;
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logic HCLK;
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logic HRESETn;
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logic [31:0] HADDR;
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logic [1:0] HTRANS;
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logic [31:0] HWDATA;
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logic HWRITE;
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logic HSEL;
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logic HREADY;
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logic HREADYOUT;
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logic [31:0] HRDATA;
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logic [15:0] GPIOIN;
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logic [15:0] GPIOOUT;
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modport DUT (input HCLK, HRESETn, HADDR, HTRANS, HWDATA, HWRITE, HSEL, HREADY, GPIOIN,
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output HREADYOUT, HRDATA, GPIOOUT);
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modport TB (input HCLK, HREADYOUT, HRDATA, GPIOOUT,
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output HRESETn, HREADY, HADDR, HTRANS, HWDATA, HWRITE, HSEL, GPIOIN);
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endinterface
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program automatic ahb_gpio_tb
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(ahb_gpio_if.TB gpioif);
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localparam [7:0] gpio_data_addr = 8'h00;
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localparam [7:0] gpio_dir_addr = 8'h04;
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localparam max_test_count = 1000;
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integer test_count;
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class gpio_stimulus;
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typedef enum bit[1:0] {
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GPIO_WRITE = 2'b00,
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GPIO_READ = 2'b01,
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GPIO_DIR = 2'b10,
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RANDOM = 2'b11
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} stimulus_op;
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rand stimulus_op gpio_op;
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rand logic HSEL;
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rand logic HWRITE;
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rand logic HREADY;
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rand logic [1:0] HTRANS;
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rand logic [31:0] HWDATA;
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rand logic [31:0] HADDR;
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rand logic [15:0] GPIOIN;
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constraint c_haddr {((gpio_op == GPIO_WRITE) && (HADDR == gpio_data_addr)) ||
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((gpio_op == GPIO_DIR) && (HADDR == gpio_dir_addr)) ||
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(gpio_op == GPIO_READ) ||
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(gpio_op == RANDOM);}
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constraint c_write {((gpio_op == GPIO_WRITE)|| (gpio_op == GPIO_DIR)) -> (HSEL && HWRITE && HREADY && (HTRANS == 2'b10));}
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constraint c_read {(gpio_op == GPIO_READ) -> (HSEL && !HWRITE && HREADY);}
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endclass
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gpio_stimulus stimulus_vals;
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covergroup cover_addr_values;
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coverpoint gpioif.HADDR {
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bins data_addr = {gpio_data_addr};
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bins dir_addr = {gpio_dir_addr};
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bins invalid_addr = default;
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}
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endgroup
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covergroup cover_wr_vals;
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coverpoint {HSEL,HWRITE,HREADY} {
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bins write = {{1,1,1}};
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bins read = {{1,0,1}};
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bins invalid = default;
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}
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endgroup
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covergroup cover_ahb_write_values;
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coverpoint gpioif.HWDATA {
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bins zero = {0};
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bins lo = {[1:7]};
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bins med = {[8:23]};
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bins hi = {[24:30]};
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bins max = {32'hFFFF};
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}
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endgroup
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covergroup cover_ahb_read_values;
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coverpoint gpioif.HRDATA {
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bins zero = {0};
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bins lo = {[1:7]};
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bins med = {[8:23]};
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bins hi = {[24:30]};
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bins max = {32'hFFFF};
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}
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endgroup
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covergroup cover_gpio_in_values;
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coverpoint gpioif.GPIOIN {
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bins zero = {0};
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bins lo = {[1:4]};
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bins med = {[5:9]};
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bins high = {[10:14]};
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bins max = {16'hFF};
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}
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endgroup
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covergroup cover_gpio_out_values;
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coverpoint gpioif.GPIOOUT {
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bins zero = {0};
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bins lo = {[1:4]};
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bins med = {[5:9]};
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bins high = {[10:14]};
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bins max = {16'hFF};
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}
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endgroup
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task deassert_reset();
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begin
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gpioif.HRESETn = 0;
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@(posedge gpioif.HCLK);
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@(posedge gpioif.HCLK);
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gpioif.HRESETn = 1;
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@(posedge gpioif.HCLK);
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end
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endtask
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initial begin
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cover_addr_values covaddr;
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cover_ahb_write_values covahbwrite;
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cover_ahb_read_values covahbread;
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cover_gpio_in_values covgpioin;
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cover_gpio_out_values covgpioout;
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covaddr = new();
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covahbwrite = new();
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covahbread = new();
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covgpioin = new();
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covgpioout = new();
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deassert_reset();
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for(test_count = 0; test_count < max_test_count;test_count++)
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begin
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@(posedge gpioif.HCLK);
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assert (stimulus_vals.randomize) else $fatal;
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gpioif.HSEL = stimulus_vals.HSEL;
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gpioif.HWRITE = stimulus_vals.HWRITE;
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gpioif.HREADY = stimulus_vals.HREADY;
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gpioif.HTRANS = stimulus_vals.HTRANS;
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gpioif.HWDATA = stimulus_vals.HWDATA;
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gpioif.HADDR = stimulus_vals.HADDR;
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gpioif.GPIOIN = stimulus_vals.GPIOIN;
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covaddr.sample();
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covahbwrite.sample();
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covgpioin.sample();
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covahbread.sample();
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covgpioout.sample();
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end
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@(posedge gpioif.HCLK);
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$finish;
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end
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endprogram
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