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add updated vga files

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Alden0012 2022-12-16 22:11:31 +00:00
parent 3c60629d48
commit 8ae5a07fca
2 changed files with 57 additions and 54 deletions
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8
rtl/AHB_VGA/dual_port_ram_sync.sv
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@ -45,7 +45,7 @@ module dual_port_ram_sync
input wire [ADDR_WIDTH-1:0] addr_a, input wire [ADDR_WIDTH-1:0] addr_a,
input wire [ADDR_WIDTH-1:0] addr_b, input wire [ADDR_WIDTH-1:0] addr_b,
input wire [DATA_WIDTH-1:0] din_a, input wire [DATA_WIDTH-1:0] din_a,
output wire [DATA_WIDTH-1:0] dout_a, output wire [DATA_WIDTH-1:0] dout_a,
output wire [DATA_WIDTH-1:0] dout_b output wire [DATA_WIDTH-1:0] dout_b
); );
@ -53,7 +53,7 @@ module dual_port_ram_sync
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0]; reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_a_reg; reg [ADDR_WIDTH-1:0] addr_a_reg;
reg [ADDR_WIDTH-1:0] addr_b_reg; reg [ADDR_WIDTH-1:0] addr_b_reg;
always @ (posedge clk) always @ (posedge clk)
begin begin
if(we) if(we)
@ -61,8 +61,8 @@ module dual_port_ram_sync
addr_a_reg <= addr_a; addr_a_reg <= addr_a;
addr_b_reg <= addr_b; addr_b_reg <= addr_b;
end end
assign dout_a = ram[addr_a_reg]; assign dout_a = ram[addr_a_reg];
assign dout_b = ram[addr_b_reg]; assign dout_b = ram[addr_b_reg];
endmodule endmodule

103
rtl/AHB_VGA/vga_sync.sv
View file

@ -1,41 +1,42 @@
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
//END USER LICENCE AGREEMENT // //END USER LICENCE AGREEMENT //
// // // //
//Copyright (c) 2012, ARM All rights reserved. // //Copyright (c) 2012, ARM All rights reserved. //
// // // //
//THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN // //THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING // //YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON // //THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR // //CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
//OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE // //OTHERWISE USING OR COPYING THE SOFTWARE EXAMPLE YOU INDICATE THAT YOU AGREE //
//TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE // //TO BE BOUND BY ALL OF THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE //
//TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO // //TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE SOFTWARE EXAMPLE TO //
//YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. // //YOU AND YOU MAY NOT INSTALL, USE OR COPY THE SOFTWARE EXAMPLE. //
// // // //
//ARM hereby grants to you, subject to the terms and conditions of this Licence,// //ARM hereby grants to you, subject to the terms and conditions of this Licence,//
//a non-exclusive, worldwide, non-transferable, copyright licence only to // //a non-exclusive, worldwide, non-transferable, copyright licence only to //
//redistribute and use in source and binary forms, with or without modification,// //redistribute and use in source and binary forms, with or without modification,//
//for academic purposes provided the following conditions are met: // //for academic purposes provided the following conditions are met: //
//a) Redistributions of source code must retain the above copyright notice, this// //a) Redistributions of source code must retain the above copyright notice, this//
//list of conditions and the following disclaimer. // //list of conditions and the following disclaimer. //
//b) Redistributions in binary form must reproduce the above copyright notice, // //b) Redistributions in binary form must reproduce the above copyright notice, //
//this list of conditions and the following disclaimer in the documentation // //this list of conditions and the following disclaimer in the documentation //
//and/or other materials provided with the distribution. // //and/or other materials provided with the distribution. //
// // // //
//THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM // //THIS SOFTWARE EXAMPLE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ARM //
//EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING // //EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING //
//WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR // //WITHOUT LIMITATION WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR //
//PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/ //PURPOSE, WITH RESPECT TO THIS SOFTWARE EXAMPLE. IN NO EVENT SHALL ARM BE LIABLE/
//FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/ //FOR ANY DIRECT, INDIRECT, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES OF ANY/
//KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE // //KIND WHATSOEVER WITH RESPECT TO THE SOFTWARE EXAMPLE. ARM SHALL NOT BE LIABLE //
//FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, // //FOR ANY CLAIMS, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, //
//TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE // //TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE //
//EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/ //EXAMPLE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE EXAMPLE. FOR THE AVOIDANCE/
// OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.// // OF DOUBT, NO PATENT LICENSES ARE BEING LICENSED UNDER THIS LICENSE AGREEMENT.//
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
module VGAInterface( module VGAInterface(
input CLK, input CLK,
input resetn,
input [7:0] COLOUR_IN, input [7:0] COLOUR_IN,
output reg [7:0] cout, output reg [7:0] cout,
output reg hs, output reg hs,
@ -43,7 +44,7 @@ module VGAInterface(
output reg [9:0] addrh, output reg [9:0] addrh,
output reg [9:0] addrv output reg [9:0] addrv
); );
// Time in Vertical Lines // Time in Vertical Lines
parameter VertTimeToPulseWidthEnd = 10'd2; parameter VertTimeToPulseWidthEnd = 10'd2;
@ -59,14 +60,16 @@ parameter HorzTimeToFrontPorchEnd = 10'd800;
wire TrigHOut, TrigDiv; wire TrigHOut, TrigDiv;
wire [9:0] HorzCount; wire [9:0] HorzCount;
wire [9:0] VertCount; wire [9:0] VertCount;
//Divide the clock frequency wire reset = ~resetn;
//Divide the clock frequency
GenericCounter #(.COUNTER_WIDTH(1), .COUNTER_MAX(1)) GenericCounter #(.COUNTER_WIDTH(1), .COUNTER_MAX(1))
FreqDivider FreqDivider
( (
.CLK(CLK), .CLK(CLK),
.RESET(1'b0), .RESET(reset),
.ENABLE_IN(1'b1), .ENABLE_IN(1'b1),
.TRIG_OUT(TrigDiv) .TRIG_OUT(TrigDiv)
); );
@ -76,22 +79,22 @@ GenericCounter #(.COUNTER_WIDTH(10), .COUNTER_MAX(HorzTimeToFrontPorchEnd))
HorzAddrCounter HorzAddrCounter
( (
.CLK(CLK), .CLK(CLK),
.RESET(1'b0), .RESET(reset),
.ENABLE_IN(TrigDiv), .ENABLE_IN(TrigDiv),
.TRIG_OUT(TrigHOut), .TRIG_OUT(TrigHOut),
.COUNT(HorzCount) .COUNT(HorzCount)
); );
//Vertical counter //Vertical counter
GenericCounter #(.COUNTER_WIDTH(10), .COUNTER_MAX(VertTimeToFrontPorchEnd)) GenericCounter #(.COUNTER_WIDTH(10), .COUNTER_MAX(VertTimeToFrontPorchEnd))
VertAddrCounter VertAddrCounter
( (
.CLK(CLK), .CLK(CLK),
.RESET(1'b0), .RESET(reset),
.ENABLE_IN(TrigHOut), .ENABLE_IN(TrigHOut),
.COUNT(VertCount) .COUNT(VertCount)
); );
//Synchronisation signals //Synchronisation signals
always@(posedge CLK) begin always@(posedge CLK) begin
if(HorzCount<HorzTimeToPulseWidthEnd) if(HorzCount<HorzTimeToPulseWidthEnd)
@ -108,20 +111,20 @@ end
//Color signals //Color signals
always@(posedge CLK) begin always@(posedge CLK) begin
if ( ( (HorzCount >= HorzTimeToBackPorchEnd ) && (HorzCount < HorzTimeToDisplayTimeEnd) ) && if ( ( (HorzCount >= HorzTimeToBackPorchEnd ) && (HorzCount < HorzTimeToDisplayTimeEnd) ) &&
( (VertCount >= VertTimeToBackPorchEnd ) && (VertCount < VertTimeToDisplayTimeEnd) ) ) ( (VertCount >= VertTimeToBackPorchEnd ) && (VertCount < VertTimeToDisplayTimeEnd) ) )
cout <= COLOUR_IN; cout <= COLOUR_IN;
else else
cout <= 8'b00000000; cout <= 8'b00000000;
end end
//output horizontal and vertical addresses //output horizontal and vertical addresses
always@(posedge CLK)begin always@(posedge CLK)begin
if ((HorzCount>HorzTimeToBackPorchEnd)&&(HorzCount<HorzTimeToDisplayTimeEnd)) if ((HorzCount>HorzTimeToBackPorchEnd)&&(HorzCount<HorzTimeToDisplayTimeEnd))
addrh<=HorzCount-HorzTimeToBackPorchEnd; addrh<=HorzCount-HorzTimeToBackPorchEnd;
else else
addrh<=10'b0000000000; addrh<=10'b0000000000;
end end
always@(posedge CLK)begin always@(posedge CLK)begin
if ((VertCount>VertTimeToBackPorchEnd)&&(VertCount<VertTimeToDisplayTimeEnd)) if ((VertCount>VertTimeToBackPorchEnd)&&(VertCount<VertTimeToDisplayTimeEnd))
addrv<=VertCount-VertTimeToBackPorchEnd; addrv<=VertCount-VertTimeToBackPorchEnd;