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Add parity generation and checking to AHBGPIO.sv

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Aadi Desai 2022-11-07 13:36:56 +00:00
parent c83b8a73f1
commit 018013d3c8
1 changed files with 40 additions and 49 deletions
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67
rtl/AHB_GPIO/AHBGPIO.sv
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@ -3,7 +3,7 @@
// // // //
//Copyright (c) 2012, ARM All rights reserved. // //Copyright (c) 2012, ARM All rights reserved. //
// // // //
//THIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN // //THIS END USER LICENCE AGREEMENT (<EFBFBD>LICENCE<EFBFBD>) IS A LEGAL AGREEMENT BETWEEN //
//YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING // //YOU AND ARM LIMITED ("ARM") FOR THE USE OF THE SOFTWARE EXAMPLE ACCOMPANYING //
//THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON // //THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE SOFTWARE EXAMPLE TO YOU ON //
//CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR // //CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY INSTALLING OR //
@ -35,31 +35,32 @@
////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////
module AHBGPIO( module AHBGPIO
input wire HCLK, ( input wire HCLK
input wire HRESETn, , input wire HRESETn
input wire [31:0] HADDR, , input wire [31:0] HADDR
input wire [1:0] HTRANS, , input wire [1:0] HTRANS
input wire [31:0] HWDATA, , input wire [31:0] HWDATA
input wire HWRITE, , input wire HWRITE
input wire HSEL, , input wire HSEL
input wire HREADY, , input wire HREADY
input wire [15:0] GPIOIN, , input wire [16:0] GPIOIN
, input wire PARITYSEL
, input wire INJECT_FAULT
//Output //Output
output wire HREADYOUT, , output wire HREADYOUT
output wire [31:0] HRDATA, , output wire [31:0] HRDATA
output wire [15:0] GPIOOUT , output wire [16:0] GPIOOUT
, output wire PARITYERR
);
);
localparam [7:0] gpio_data_addr = 8'h00; localparam [7:0] gpio_data_addr = 8'h00;
localparam [7:0] gpio_dir_addr = 8'h04; localparam [7:0] gpio_dir_addr = 8'h04;
reg [15:0] gpio_dataout; reg [15:0] gpio_dataout;
reg gpio_parityout;
reg [15:0] gpio_datain; reg [15:0] gpio_datain;
reg gpio_parityerr;
reg [15:0] gpio_dir; reg [15:0] gpio_dir;
reg [15:0] gpio_data_next; reg [15:0] gpio_data_next;
reg [31:0] last_HADDR; reg [31:0] last_HADDR;
@ -73,52 +74,42 @@ module AHBGPIO(
// Set Registers from address phase // Set Registers from address phase
always @(posedge HCLK) always @(posedge HCLK)
begin if(HREADY) begin
if(HREADY)
begin
last_HADDR <= HADDR; last_HADDR <= HADDR;
last_HTRANS <= HTRANS; last_HTRANS <= HTRANS;
last_HWRITE <= HWRITE; last_HWRITE <= HWRITE;
last_HSEL <= HSEL; last_HSEL <= HSEL;
end end
end
// Update in/out switch // Update in/out switch
always @(posedge HCLK, negedge HRESETn) always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn) if(!HRESETn)
begin
gpio_dir <= 16'h0000; gpio_dir <= 16'h0000;
end
else if ((last_HADDR[7:0] == gpio_dir_addr) & last_HSEL & last_HWRITE & last_HTRANS[1]) else if ((last_HADDR[7:0] == gpio_dir_addr) & last_HSEL & last_HWRITE & last_HTRANS[1])
gpio_dir <= HWDATA[15:0]; gpio_dir <= HWDATA[15:0];
end
// Update output value // Update output value
always @(posedge HCLK, negedge HRESETn) always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn) if(!HRESETn)
begin {gpio_parityout, gpio_dataout} <= 17'd0;
gpio_dataout <= 16'h0000; else if ((gpio_dir == 16'h0001) & (last_HADDR[7:0] == gpio_data_addr) & last_HSEL & last_HWRITE & last_HTRANS[1]) begin
end
else if ((gpio_dir == 16'h0001) & (last_HADDR[7:0] == gpio_data_addr) & last_HSEL & last_HWRITE & last_HTRANS[1])
gpio_dataout <= HWDATA[15:0]; gpio_dataout <= HWDATA[15:0];
gpio_parityout <= ~^{HWDATA[15:0],PARITYSEL,INJECT_FAULT};
end end
// Update input value // Update input value
always @(posedge HCLK, negedge HRESETn) always @(posedge HCLK, negedge HRESETn)
begin
if(!HRESETn) if(!HRESETn)
begin
gpio_datain <= 16'h0000; gpio_datain <= 16'h0000;
else if (gpio_dir == 16'h0000) begin
gpio_datain <= GPIOIN[15:0];
gpio_parityerr <= ~^{GPIOIN,PARITYSEL,INJECT_FAULT};
end end
else if (gpio_dir == 16'h0000)
gpio_datain <= GPIOIN;
else if (gpio_dir == 16'h0001) else if (gpio_dir == 16'h0001)
gpio_datain <= GPIOOUT; gpio_datain <= GPIOOUT;
end
assign HRDATA[15:0] = gpio_datain; assign HRDATA[15:0] = gpio_datain;
assign GPIOOUT = gpio_dataout; assign GPIOOUT = {gpio_parityout, gpio_dataout};
assign PARITYERR = gpio_parityerr;
endmodule endmodule