supleed2/ELEC60015-HLP-CW
1
0
Fork 0
mirror of https://github.com/supleed2/ELEC60015-HLP-CW.git synced 2024-12-22 21:45:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix a rightangle weird case

Browse source
This commit is contained in:
Philip Puk 2022-03-16 19:33:16 +00:00
parent dac0f1bdcc
commit c43910e438
1 changed files with 6 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/Renderer/DrawBlock/BusWire.fs
View file

@ -317,7 +317,7 @@ let pp segs (model: Model)=
|> String.concat ";" |> String.concat ";"
let ppRISeg riseg= let ppRISeg riseg=
printfn $"Index:{riseg.Index},Dir:{riseg.Dir},Length:{riseg.Length}" printfn $"Index:{riseg.Index},Dir:{riseg.Dir},Length:{riseg.Length},Draggable:{riseg.Draggable}"
riseg riseg
//-------------------------------Implementation code----------------------------// //-------------------------------Implementation code----------------------------//
@ -382,7 +382,7 @@ let initialWireVerticesFromPorts (startPort:XYPos) (endPort:XYPos) (routetype:ro
{X = endX; Y = endY} {X = endX; Y = endY}
], false // not left to right ], false // not left to right
|Rightangle -> |Rightangle ->
if (endX-startX >= Wire.stickLength) && (endY-startY>=Wire.stickLength) then if (abs(endX-startX) >= Wire.stickLength) && (abs(endY-startY)>=Wire.stickLength) then
[ [
{X = startX; Y = startY}; {X = startX; Y = startY};
{X = startX + Wire.stickLength; Y = startY}; {X = startX + Wire.stickLength; Y = startY};
@ -490,13 +490,12 @@ let convertVerticesToASegs connId (isLeftToRight: bool) routetype rotation (yref
| _ -> true | _ -> true
| Sameside-> | Sameside->
match index with match index with
| 2 -> true | 0 | 6 -> false
| 3 | 4 -> not isLeftToRight | _ -> true
| _ -> false
| Rightangle-> | Rightangle->
match index with match index with
| 3 | 4 -> not isLeftToRight | 0 | 6 -> false
| _ -> false | _ -> true
let flipdir= let flipdir=
function | Horizontal -> Vertical function | Horizontal -> Vertical