From c43910e438e5513be6815d54738ed8ffad917e8a Mon Sep 17 00:00:00 2001
From: Philip Puk <yanhoipuk@yahoo.com>
Date: Wed, 16 Mar 2022 19:33:16 +0000
Subject: [PATCH] fix a rightangle weird case

---
 src/Renderer/DrawBlock/BusWire.fs | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/Renderer/DrawBlock/BusWire.fs b/src/Renderer/DrawBlock/BusWire.fs
index e6902d2..57a868d 100644
--- a/src/Renderer/DrawBlock/BusWire.fs
+++ b/src/Renderer/DrawBlock/BusWire.fs
@@ -317,7 +317,7 @@ let pp segs (model: Model)=
     |> String.concat ";"
 
 let ppRISeg riseg=
-    printfn $"Index:{riseg.Index},Dir:{riseg.Dir},Length:{riseg.Length}"
+    printfn $"Index:{riseg.Index},Dir:{riseg.Dir},Length:{riseg.Length},Draggable:{riseg.Draggable}"
     riseg
 
 //-------------------------------Implementation code----------------------------//
@@ -382,7 +382,7 @@ let initialWireVerticesFromPorts (startPort:XYPos) (endPort:XYPos) (routetype:ro
                 {X = endX; Y = endY}
             ], false // not left to right
     |Rightangle -> 
-        if (endX-startX >= Wire.stickLength) && (endY-startY>=Wire.stickLength) then
+        if (abs(endX-startX) >= Wire.stickLength) && (abs(endY-startY)>=Wire.stickLength) then
             [ 
                 {X = startX; Y = startY};
                 {X = startX + Wire.stickLength; Y = startY};
@@ -490,13 +490,12 @@ let convertVerticesToASegs connId (isLeftToRight: bool) routetype rotation (yref
                     | _ -> true
             | Sameside-> 
                 match index with
-                    | 2 -> true
-                    | 3 | 4 -> not isLeftToRight 
-                    | _ -> false
+                    | 0 | 6 -> false
+                    | _ -> true
             | Rightangle->
                 match index with
-                    | 3 | 4 ->  not isLeftToRight 
-                    | _ -> false
+                    | 0 | 6 -> false
+                    | _ -> true
 
     let flipdir=
         function | Horizontal -> Vertical