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https://github.com/supleed2/ELEC60015-HLP-CW.git
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fix a rightangle weird case
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@ -317,7 +317,7 @@ let pp segs (model: Model)=
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|> String.concat ";"
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|> String.concat ";"
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let ppRISeg riseg=
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let ppRISeg riseg=
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printfn $"Index:{riseg.Index},Dir:{riseg.Dir},Length:{riseg.Length}"
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printfn $"Index:{riseg.Index},Dir:{riseg.Dir},Length:{riseg.Length},Draggable:{riseg.Draggable}"
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riseg
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riseg
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//-------------------------------Implementation code----------------------------//
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//-------------------------------Implementation code----------------------------//
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@ -382,7 +382,7 @@ let initialWireVerticesFromPorts (startPort:XYPos) (endPort:XYPos) (routetype:ro
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{X = endX; Y = endY}
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{X = endX; Y = endY}
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], false // not left to right
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], false // not left to right
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|Rightangle ->
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|Rightangle ->
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if (endX-startX >= Wire.stickLength) && (endY-startY>=Wire.stickLength) then
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if (abs(endX-startX) >= Wire.stickLength) && (abs(endY-startY)>=Wire.stickLength) then
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[
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[
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{X = startX; Y = startY};
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{X = startX; Y = startY};
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{X = startX + Wire.stickLength; Y = startY};
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{X = startX + Wire.stickLength; Y = startY};
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@ -490,13 +490,12 @@ let convertVerticesToASegs connId (isLeftToRight: bool) routetype rotation (yref
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| _ -> true
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| _ -> true
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| Sameside->
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| Sameside->
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match index with
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match index with
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| 2 -> true
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| 0 | 6 -> false
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| 3 | 4 -> not isLeftToRight
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| _ -> true
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| _ -> false
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| Rightangle->
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| Rightangle->
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match index with
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match index with
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| 3 | 4 -> not isLeftToRight
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| 0 | 6 -> false
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| _ -> false
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| _ -> true
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let flipdir=
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let flipdir=
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function | Horizontal -> Vertical
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function | Horizontal -> Vertical
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