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57 lines
938 B
Verilog
57 lines
938 B
Verilog
`timescale 1 ns / 100 ps
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module tb ();
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//Inputs to DUT are reg type
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reg [31:0] dataa;
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reg [31:0] datab;
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//Output from DUT is wire type
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wire [31:0] result;
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//Instantiate the DUT
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//mul refers to the verilog module defined by the LPM_MULT ip
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mul unit(
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.dataa(dataa),
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.datab(datab),
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.result(result)
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);
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// ---- If a clock is required, see below ----
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// //Create a 50MHz clock
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// always
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// #10 clk = ~clk;
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// -----------------------
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//Initial Block
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initial
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begin
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$display($time, " << Starting Simulation >> ");
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// intialise/set input
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// clk = 1'b0;
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// If using a clock
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// @(posedge clk);
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// Wait 10 cycles (corresponds to timescale at the top)
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#10
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// set dataa and datab
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dataa <= 32'd1;
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datab <= 32'd2;
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#10
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dataa <= 32'd332;
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datab <= 32'd22;
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#10
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dataa <= 32'd2;
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datab <= 32'd23;
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#10
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$display($time, "<< Simulation Complete >>");
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$stop;
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end
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endmodule
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