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29 lines
1.2 KiB
Verilog
29 lines
1.2 KiB
Verilog
// Copyright (C) 2020 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details, at
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// https://fpgasoftware.intel.com/eula.
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// PROGRAM "Quartus Prime"
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// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
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// CREATED "Tue Mar 22 12:03:47 2022"
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module lpm_constant_1(result);
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output [31:0] result;
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lpm_constant lpm_instance(.result(result));
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defparam lpm_instance.LPM_CVALUE = 32'b00000000000000000000000000000000;
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defparam lpm_instance.LPM_WIDTH = 32;
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endmodule
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