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17 lines
781 B
Tcl
17 lines
781 B
Tcl
#Update -period with clock period (in nanoseconds) of the clock driving the fpga
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create_clock -name sopc_clk -period 20 [get_ports iCLK_50]
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#Setting LED outputs as false path, since no timing requirement
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set_false_path -from * -to [get_ports oLEDG[*]]
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#Constraining JTAG interface
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#TCK port
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create_clock -name altera_reserved_tck -period 100 [get_ports altera_reserved_tck]
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#cut all paths to and from tck
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set_clock_groups -exclusive -group [get_clocks altera_reserved_tck]
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#constrain the TDI port
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set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]
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#constrain the TMS port
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set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]
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#constrain the TDO port
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set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo] |