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8 lines
196 B
Verilog
8 lines
196 B
Verilog
module fp_div128 (
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input [31:0] dataa,
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output [31:0] result
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);
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wire [7:0] NewExp;
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assign NewExp = dataa[30:23]-7;
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assign result = (dataa[30:23]<=6) ? 0 : {dataa[31],NewExp,dataa[22:0]};
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endmodule |