mirror of
https://github.com/supleed2/ELEC60011-DSD-CW.git
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123 lines
2.4 KiB
Verilog
123 lines
2.4 KiB
Verilog
// Copyright (C) 2020 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details, at
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// https://fpgasoftware.intel.com/eula.
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// PROGRAM "Quartus Prime"
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// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
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// CREATED "Sun Mar 27 15:17:39 2022"
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module dualfunction_t(
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clk,
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reset,
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en,
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start,
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dataa,
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datab,
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done,
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result
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);
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input wire clk;
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input wire reset;
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input wire en;
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input wire start;
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input wire [31:0] dataa;
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input wire [31:0] datab;
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output reg done;
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output wire [31:0] result;
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wire [31:0] SYNTHESIZED_WIRE_0;
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wire [31:0] SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_3;
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wire SYNTHESIZED_WIRE_9;
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wire SYNTHESIZED_WIRE_5;
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reg DFF_inst4;
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assign SYNTHESIZED_WIRE_9 = 1;
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fullfunction_t b2v_inst(
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.clk(clk),
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.reset(reset),
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.en(en),
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.start(start),
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.dataa(dataa),
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.done(SYNTHESIZED_WIRE_2),
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.result(SYNTHESIZED_WIRE_0));
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fullfunction_t b2v_inst1(
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.clk(clk),
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.reset(reset),
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.en(en),
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.start(start),
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.dataa(datab),
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.done(SYNTHESIZED_WIRE_3),
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.result(SYNTHESIZED_WIRE_1));
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fp_add b2v_inst2(
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.clk(clk),
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.areset(reset),
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.en(en),
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.a(SYNTHESIZED_WIRE_0),
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.b(SYNTHESIZED_WIRE_1),
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.q(result));
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assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_3;
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always@(posedge clk or negedge SYNTHESIZED_WIRE_9 or negedge SYNTHESIZED_WIRE_9)
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begin
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if (!SYNTHESIZED_WIRE_9)
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begin
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DFF_inst4 <= 0;
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end
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else
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if (!SYNTHESIZED_WIRE_9)
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begin
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DFF_inst4 <= 1;
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end
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else
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begin
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DFF_inst4 <= SYNTHESIZED_WIRE_5;
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end
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end
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always@(posedge clk or negedge SYNTHESIZED_WIRE_9 or negedge SYNTHESIZED_WIRE_9)
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begin
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if (!SYNTHESIZED_WIRE_9)
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begin
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done <= 0;
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end
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else
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if (!SYNTHESIZED_WIRE_9)
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begin
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done <= 1;
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end
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else
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begin
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done <= DFF_inst4;
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end
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end
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endmodule
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