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74 lines
2.1 KiB
Verilog
74 lines
2.1 KiB
Verilog
module mips_cpu_bus_tb;
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parameter INSTR_INIT_FILE = "";
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parameter DATA_INIT_FILE = "";
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parameter TESTCASE = "";
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parameter TIMEOUT_CYCLES = 100; // Timeout cycles are higher to account for memory stall delays
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logic clk, reset, active, write, read, waitrequest;
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logic[31:0] address, register_v0, writedata, readdata;
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logic[3:0] byteenable;
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mips_cpu_bus_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) memInst( //Avalon memory mapped bus controller (slave)
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.clk(clk), // clk input to mem
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.reset(reset), // reset input to stall mem during cpu reset
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.address(address), // addr input to mem
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.write(write), // write flag input
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.read(read), // read flag input
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.waitrequest(waitrequest), // mem stall output
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.writedata(writedata), // data to be written
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.byteenable(byteenable), // byteenable bus for writes
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.readdata(readdata) // read output port
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);
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mips_cpu_bus cpuInst(
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.clk(clk), // clk input to cpu wrapper
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.reset(reset), // reset input
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.active(active), // active output flag
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.register_v0(register_v0), // debug $2 or $v0 output bus
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.address(address), // mem addr output
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.write(write), // mem write output flag
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.read(read), // mem read output flag
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.waitrequest(waitrequest), // mem stall input flag
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.writedata(writedata), // data to write to mem output
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.byteenable(byteenable), // bytes to write output
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.readdata(readdata) // data from mem input
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);
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// Setup and clock
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initial begin
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$dumpfile(TESTCASE);
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$dumpvars(0,mips_cpu_bus_tb);
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clk=0;
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repeat (TIMEOUT_CYCLES) begin
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#10;
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clk = !clk;
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#10;
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clk = !clk;
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end
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$fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES);
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end
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initial begin
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reset <= 1;
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@(posedge clk);
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reset <= 0;
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@(posedge clk);
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assert(active==1)
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else $display("TB : CPU did not set active=1 after reset.");
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while (active) begin
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@(posedge clk);
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end
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@(posedge clk);
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$display("TB: CPU Halt; active=0");
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$display("Output:");
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$display("%d",register_v0);
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$finish;
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end
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endmodule |