ELEC50010-IAC-CW/testbench/mips_cpu_bus_tb.v

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module mips_cpu_bus_tb;
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parameter INSTR_INIT_FILE = "";
parameter DATA_INIT_FILE = "";
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parameter TESTCASE = "";
parameter TIMEOUT_CYCLES = 100; // Timeout cycles are higher to account for memory stall delays
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logic clk, reset, active, write, read, waitrequest;
logic[31:0] address, register_v0, writedata, readdata;
logic[3:0] byteenable;
mips_cpu_bus_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) memInst( //Avalon memory mapped bus controller (slave)
.clk(clk), // clk input to mem
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.reset(reset), // reset input to stall mem during cpu reset
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.address(address), // addr input to mem
.write(write), // write flag input
.read(read), // read flag input
.waitrequest(waitrequest), // mem stall output
.writedata(writedata), // data to be written
.byteenable(byteenable), // byteenable bus for writes
.readdata(readdata) // read output port
);
mips_cpu_bus cpuInst(
.clk(clk), // clk input to cpu wrapper
.reset(reset), // reset input
.active(active), // active output flag
.register_v0(register_v0), // debug $2 or $v0 output bus
.address(address), // mem addr output
.write(write), // mem write output flag
.read(read), // mem read output flag
.waitrequest(waitrequest), // mem stall input flag
.writedata(writedata), // data to write to mem output
.byteenable(byteenable), // bytes to write output
.readdata(readdata) // data from mem input
);
// Setup and clock
initial begin
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$dumpfile(TESTCASE);
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$dumpvars(0,mips_cpu_bus_tb);
clk=0;
repeat (TIMEOUT_CYCLES) begin
#10;
clk = !clk;
#10;
clk = !clk;
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end
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$fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES);
end
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initial begin
reset <= 1;
@(posedge clk);
reset <= 0;
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@(posedge clk);
assert(active==1)
else $display("TB : CPU did not set active=1 after reset.");
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while (active) begin
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@(posedge clk);
end
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@(posedge clk);
$display("TB: CPU Halt; active=0");
$display("Output:");
$display("%d",register_v0);
$finish;
end
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endmodule