mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
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108 lines
3.5 KiB
Plaintext
108 lines
3.5 KiB
Plaintext
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2019 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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(header "symbol" (version "1.2"))
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(symbol
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(rect 16 16 264 208)
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(text "REGISTERS" (rect 5 0 51 10)(font "Tahoma" (font_size 6)))
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(text "inst" (rect 8 171 24 188)(font "Intel Clear" ))
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(port
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(pt 0 32)
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(input)
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(text "clk" (rect 0 0 16 19)(font "Intel Clear" (font_size 8)))
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(text "clk" (rect 21 27 37 46)(font "Intel Clear" (font_size 8)))
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(line (pt 0 32)(pt 16 32))
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)
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(port
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(pt 0 48)
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(input)
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(text "rst" (rect 0 0 15 19)(font "Intel Clear" (font_size 8)))
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(text "rst" (rect 21 43 36 62)(font "Intel Clear" (font_size 8)))
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(line (pt 0 48)(pt 16 48))
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)
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(port
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(pt 0 64)
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(input)
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(text "readreg1[4:0}" (rect 0 0 82 19)(font "Intel Clear" (font_size 8)))
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(text "readreg1[4:0}" (rect 21 59 103 78)(font "Intel Clear" (font_size 8)))
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(line (pt 0 64)(pt 16 64))
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)
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(port
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(pt 0 80)
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(input)
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(text "readreg2[4:0]" (rect 0 0 82 19)(font "Intel Clear" (font_size 8)))
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(text "readreg2[4:0]" (rect 21 75 103 94)(font "Intel Clear" (font_size 8)))
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|
(line (pt 0 80)(pt 16 80))
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)
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|
(port
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(pt 0 96)
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|
(input)
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(text "writereg[4:0]" (rect 0 0 76 19)(font "Intel Clear" (font_size 8)))
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|
(text "writereg[4:0]" (rect 21 91 97 110)(font "Intel Clear" (font_size 8)))
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|
(line (pt 0 96)(pt 16 96))
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)
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(port
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(pt 0 112)
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|
(input)
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(text "writedata[31:0]" (rect 0 0 93 19)(font "Intel Clear" (font_size 8)))
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(text "writedata[31:0]" (rect 21 107 114 126)(font "Intel Clear" (font_size 8)))
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(line (pt 0 112)(pt 16 112))
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)
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(port
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(pt 0 128)
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(input)
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(text "regwrite" (rect 0 0 48 19)(font "Intel Clear" (font_size 8)))
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(text "regwrite" (rect 21 123 69 142)(font "Intel Clear" (font_size 8)))
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(line (pt 0 128)(pt 16 128))
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)
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(port
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(pt 0 144)
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(input)
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(text "opcode[5:0]" (rect 0 0 71 19)(font "Intel Clear" (font_size 8)))
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(text "opcode[5:0]" (rect 21 139 92 158)(font "Intel Clear" (font_size 8)))
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(line (pt 0 144)(pt 16 144))
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)
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|
(port
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(pt 248 32)
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|
(output)
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(text "readdata1[31:0]" (rect 0 0 99 19)(font "Intel Clear" (font_size 8)))
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(text "readdata1[31:0]" (rect 128 27 227 46)(font "Intel Clear" (font_size 8)))
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(line (pt 248 32)(pt 232 32))
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)
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|
(port
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(pt 248 48)
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|
(output)
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(text "readdata2[31:0]" (rect 0 0 99 19)(font "Intel Clear" (font_size 8)))
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(text "readdata2[31:0]" (rect 128 43 227 62)(font "Intel Clear" (font_size 8)))
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(line (pt 248 48)(pt 232 48))
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)
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(port
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(pt 248 64)
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(output)
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(text "regv0" (rect 0 0 34 19)(font "Intel Clear" (font_size 8)))
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(text "regv0" (rect 193 59 227 78)(font "Intel Clear" (font_size 8)))
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(line (pt 248 64)(pt 232 64))
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)
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(drawing
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(rectangle (rect 16 16 232 176))
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)
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)
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