jl7719
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a31d41512b
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Rename all instruction mem init files to .instr.txt
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2020-12-18 12:42:58 +00:00 |
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theexecutor13
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bcc05cd061
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-18 10:07:54 +00:00 |
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theexecutor13
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3f8393a404
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add some testcases
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2020-12-18 10:07:42 +00:00 |
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jl7719
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f3779e1cc3
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Fix div-5 testcase minor error
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2020-12-18 09:24:58 +00:00 |
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jl7719
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2a7b9c2c49
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-18 09:22:27 +00:00 |
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jl7719
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47a452cd6d
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Fix div input testcases 3,4,5
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2020-12-18 09:20:00 +00:00 |
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Ibrahim
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579dc5e008
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fixed one test case
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2020-12-18 09:10:46 +00:00 |
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Ibrahim
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48e0cdfbb6
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added edge cases these don't pass - please check
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2020-12-18 08:48:51 +00:00 |
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Aadi Desai
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1be11d6c19
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Add second store halfword testcase
Checks that only half the word is written using load word after store halfword
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2020-12-17 10:00:18 -08:00 |
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Aadi Desai
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c8344184b2
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Fix sb, sh testcases
Tried to write to instr mem + typo
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2020-12-17 09:41:55 -08:00 |
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theexecutor13
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6c400f3567
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uploading log.txt weirdness testcase
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2020-12-17 14:31:33 +00:00 |
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theexecutor13
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7fcc2486cb
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cleanup
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2020-12-17 13:37:00 +00:00 |
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theexecutor13
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ab13c84ef5
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testing branch delay slot
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2020-12-17 12:03:30 +00:00 |
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jl7719
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697b6e0a9e
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Update some testcases for branch delay slots
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2020-12-16 17:13:39 +00:00 |
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Aadi Desai
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252f630162
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Cleanup
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2020-12-16 15:40:21 +00:00 |
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Aadi Desai
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1a413d9686
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Merge branch 'main' into jl7719
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2020-12-16 15:40:07 +00:00 |
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jl7719
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ebe33ce56a
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Passes all tests
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2020-12-16 15:29:04 +00:00 |
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Jeevaha Coelho
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7185f7e7e6
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Fixed BGEZAL
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2020-12-16 07:00:46 -08:00 |
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Jeevaha Coelho
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2673e23137
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FIxed PC!
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2020-12-16 05:21:57 -08:00 |
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jl7719
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ad68ab0974
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Debugging and debugging
PC, Jump instr, branches
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2020-12-16 12:29:22 +00:00 |
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jl7719
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0891f7e653
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Debug mult/div to work
it works now
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2020-12-16 08:38:46 +00:00 |
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yhp19
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07d32e9baf
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fixed input file plz document ur change in reference.txt
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2020-12-16 12:27:48 +08:00 |
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yhp19
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cc5d2bbeab
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changes to input files
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2020-12-16 00:57:46 +08:00 |
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jl7719
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b812399844
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Fix to allow multiple testcases for each instruction
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2020-12-15 15:06:04 +00:00 |
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Ibrahim
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adb4b5d6fd
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created seperate division testcases, fived srlv, sllu, srav & added sh (forgot this instruction previously)
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2020-12-15 13:42:09 +00:00 |
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Ibrahim
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26ccff5057
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Merge branch 'jl7719' of https://github.com/supleed2/AM04_CPU into main
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2020-12-15 13:38:04 +00:00 |
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ppuk
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2030a186cc
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changed bltzal input txt
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2020-12-15 08:56:23 +00:00 |
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jl7719
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63abcf671a
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Tidy up and change bash to ./
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2020-12-14 17:49:30 +00:00 |
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theexecutor13
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6519be9a9e
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Update reference.txt
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2020-12-14 23:59:08 +08:00 |
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theexecutor13
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d72676c30c
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Update bltzal.txt
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2020-12-14 23:58:08 +08:00 |
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jl7719
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f882d1e361
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Test different inputs for lb, lbu
it works
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2020-12-13 15:16:53 +09:00 |
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jl7719
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943745a1e0
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Tested all that can be tested for now
Mult/Div, Branch/Jump Linking, J needs implementation before testing and store to be tested when switched to bus
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2020-12-13 14:40:16 +09:00 |
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jl7719
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c31344c55f
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More testcases, testing, debugging
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2020-12-13 01:25:36 +09:00 |
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yhp19
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276f7f8216
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Added ref files for j and load instructions
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2020-12-12 23:59:04 +08:00 |
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yhp19
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ab27fcaed3
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Reference txt now in reference folders
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2020-12-12 23:46:42 +08:00 |
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yhp19
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69cd711cfc
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Added load instruction txt and data.txt
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2020-12-12 23:39:00 +08:00 |
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jl7719
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14ad7fa0ce
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Update program counter
Logic for instructions with linking not implemented. Can do basic branch delay slots. More left to do with return register
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2020-12-12 15:59:14 +09:00 |
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jl7719
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3594365a25
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Create branch jl7719
Can test for normal pc incrementing instr
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2020-12-11 19:45:13 +09:00 |
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yhp19
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2c5b3ad604
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Merge branch 'main' of https://github.com/supleed2/AM04_CPU into main
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2020-12-11 15:54:45 +08:00 |
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yhp19
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47e0f42f92
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added load instructions
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2020-12-11 15:54:23 +08:00 |
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jl7719
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7ffd8fb400
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Add testcases and ref outputs for addiu, and, andi
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2020-12-11 15:17:43 +09:00 |
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Ibrahim
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1bf7b5d40e
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All instructions except load finished - some test cases may need changing upon review
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2020-12-10 19:39:04 +00:00 |
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jl7719
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c93473a54d
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Update test_mips_cpu_harvard.sh
Outputs Pass/Fail by comparing to INSTR.ref.txt files (need to add these per instr)
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2020-12-10 17:24:40 +09:00 |
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yhp19
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db344b3150
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added div and instruction testcase and minor adjustment on bl instructions
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2020-12-10 13:51:54 +08:00 |
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Ibrahim
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0be5617371
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75% done - need to redo arithemtic operation to test edge cases & do certain instr by hand
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2020-12-09 20:17:58 +00:00 |
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yhp19
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31ad264fac
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updated with .txt files
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2020-12-10 00:57:31 +08:00 |
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theexecutor13
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315e5af32c
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Update reference.txt
Fixed branch instruction test case in ref.txt
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2020-12-10 00:41:19 +08:00 |
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theexecutor13
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b17158489f
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Added jump type testcase in ref.txt
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2020-12-10 00:10:38 +08:00 |
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jl7719
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7e6bc7c370
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Update branch testcases
Reference file is not updated
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2020-12-09 23:21:45 +09:00 |
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jl7719
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c5aed43ab4
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Update to test each instruction with a small memory
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2020-12-09 16:47:58 +09:00 |
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