PC logic updated

PC now has a delay into instr_mem to match MIPS32 spec and pc resets/initialises to MIPS32 reset vector
This commit is contained in:
Aadi Desai 2020-12-02 17:23:28 +00:00
parent 10af46a352
commit f2f8e05010
2 changed files with 25 additions and 38 deletions

View file

@ -33,7 +33,7 @@ logic[31:0] Jump_addr = {{pc_curr+4}[31:28], instr_readdata[25:0], 2'b00};
logic PCSrc = Branch && ALUZero;
//Instruction MEM
assign instr_address = pc_curr;
assign instr_address = pc_delay;
//deconstruction of instruction :)
logic[5:0] opcode = instr_readdata[31:26];
@ -56,8 +56,13 @@ assign data_writedata = read_data2; //data to be written comes from reg read bus
//Writeback logic
logic[31:0] writeback = MemtoReg==2'b10 ? {pc_curr+4} : MemtoReg==2'b01 ? data_readdata : ALUOut;
always_ff @(posedge clk) begin
pc_delay <= pc_curr;
end
pc pc(
.clk(clk),
.rst(reset),
.pc_in(pc_next),
.pc_out(pc_curr)
);

View file

@ -1,43 +1,25 @@
module ProgramCounter(
module pc(
input logic clk,
input logic rst,
input logic[31:0] pc_in,
output logic[31:0] pc_out
);
input logic rst,
input logic clk,
input logic[31:0] pcWriteAddr,
input logic pcWriteEn,
reg[31:0] pc_curr;
output logic[31:0] pcRes,
initial begin
pc_curr = 32'hBFC00000;
end : initial
);
logic[31:0] pcIncr;
initial begin
pcRes <= 32'h00000000;
always_comb begin
if (rst) begin
pc_curr = 32'hBFC00000;
end
pc_out = pc_curr;
end
always_comb begin
pcIncr = pcRes + 32'h00000004
end
always_ff @(posedge clk) begin
pc_curr <= pc_in;
end
always @(posedge clk)
begin
if (rst == 1)
begin
pcRes <= 32'h00000000;
end
else
begin
if (pcWriteEn == 1) begin
pcRes <= pcWriteAddr;
end
else begin
pcRes <= pcIncr;
end
end
$display("pc = %h",pcRes);
end
endmodule
endmodule : pc