diff --git a/rtl/mips_cpu_harvard.v b/rtl/mips_cpu_harvard.v
index 15649b1..ac98748 100644
--- a/rtl/mips_cpu_harvard.v
+++ b/rtl/mips_cpu_harvard.v
@@ -33,7 +33,7 @@ logic[31:0] Jump_addr = {{pc_curr+4}[31:28], instr_readdata[25:0], 2'b00};
 logic PCSrc = Branch && ALUZero;
 
 //Instruction MEM
-assign instr_address = pc_curr;
+assign instr_address = pc_delay;
 
 //deconstruction of instruction :)
 logic[5:0] opcode = instr_readdata[31:26];
@@ -56,8 +56,13 @@ assign data_writedata = read_data2; //data to be written comes from reg read bus
 //Writeback logic
 logic[31:0] writeback = MemtoReg==2'b10 ? {pc_curr+4} : MemtoReg==2'b01 ? data_readdata : ALUOut;
 
+always_ff @(posedge clk) begin
+    pc_delay <= pc_curr;
+end
+
 pc pc(
 .clk(clk),
+.rst(reset),
 .pc_in(pc_next),
 .pc_out(pc_curr)
 );
diff --git a/rtl/mips_cpu_pc.v b/rtl/mips_cpu_pc.v
index c2580a8..5f1b77c 100644
--- a/rtl/mips_cpu_pc.v
+++ b/rtl/mips_cpu_pc.v
@@ -1,43 +1,25 @@
-module ProgramCounter(
+module pc(
+input logic clk,
+input logic rst,
+input logic[31:0] pc_in,
+output logic[31:0] pc_out
+);
 
-	input logic			rst, 
-	input logic			clk, 
-	
-	input logic[31:0]	pcWriteAddr,
-	input logic			pcWriteEn,
+reg[31:0] pc_curr;
 
-	output logic[31:0]  pcRes,
+initial begin
+	pc_curr = 32'hBFC00000;
+end : initial
 
-	);
-
-	logic[31:0] pcIncr;
-
-	initial begin
-	
-		pcRes <= 32'h00000000;
+always_comb begin
+	if (rst) begin
+		pc_curr = 32'hBFC00000;
 	end
+	pc_out = pc_curr;
+end
 
-	always_comb begin
-		pcIncr = pcRes + 32'h00000004
-	end
+always_ff @(posedge clk) begin
+	pc_curr <= pc_in;
+end
 
-    always @(posedge clk)
-    begin
-    	if (rst == 1)
-    	begin
-    		pcRes <= 32'h00000000;
-    	end
-    	else
-    	begin
-			if (pcWriteEn == 1) begin
-				pcRes <= pcWriteAddr;
-			end
-			else begin
-				pcRes <= pcIncr;
-			end
-    	end
-
-		$display("pc = %h",pcRes);
-    end
-
-endmodule
\ No newline at end of file
+endmodule : pc
\ No newline at end of file