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https://github.com/supleed2/ELEC50010-IAC-CW.git
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PC logic updated
PC now has a delay into instr_mem to match MIPS32 spec and pc resets/initialises to MIPS32 reset vector
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@ -33,7 +33,7 @@ logic[31:0] Jump_addr = {{pc_curr+4}[31:28], instr_readdata[25:0], 2'b00};
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logic PCSrc = Branch && ALUZero;
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logic PCSrc = Branch && ALUZero;
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//Instruction MEM
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//Instruction MEM
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assign instr_address = pc_curr;
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assign instr_address = pc_delay;
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//deconstruction of instruction :)
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//deconstruction of instruction :)
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logic[5:0] opcode = instr_readdata[31:26];
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logic[5:0] opcode = instr_readdata[31:26];
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@ -56,8 +56,13 @@ assign data_writedata = read_data2; //data to be written comes from reg read bus
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//Writeback logic
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//Writeback logic
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logic[31:0] writeback = MemtoReg==2'b10 ? {pc_curr+4} : MemtoReg==2'b01 ? data_readdata : ALUOut;
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logic[31:0] writeback = MemtoReg==2'b10 ? {pc_curr+4} : MemtoReg==2'b01 ? data_readdata : ALUOut;
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always_ff @(posedge clk) begin
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pc_delay <= pc_curr;
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end
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pc pc(
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pc pc(
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.clk(clk),
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.clk(clk),
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.rst(reset),
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.pc_in(pc_next),
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.pc_in(pc_next),
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.pc_out(pc_curr)
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.pc_out(pc_curr)
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);
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);
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@ -1,43 +1,25 @@
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module ProgramCounter(
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module pc(
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input logic clk,
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input logic rst,
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input logic[31:0] pc_in,
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output logic[31:0] pc_out
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);
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input logic rst,
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reg[31:0] pc_curr;
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input logic clk,
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input logic[31:0] pcWriteAddr,
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initial begin
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input logic pcWriteEn,
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pc_curr = 32'hBFC00000;
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end : initial
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output logic[31:0] pcRes,
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always_comb begin
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if (rst) begin
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);
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pc_curr = 32'hBFC00000;
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logic[31:0] pcIncr;
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initial begin
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pcRes <= 32'h00000000;
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end
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end
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pc_out = pc_curr;
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end
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always_comb begin
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always_ff @(posedge clk) begin
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pcIncr = pcRes + 32'h00000004
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pc_curr <= pc_in;
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end
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end
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always @(posedge clk)
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endmodule : pc
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begin
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if (rst == 1)
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begin
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pcRes <= 32'h00000000;
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end
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else
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begin
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if (pcWriteEn == 1) begin
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pcRes <= pcWriteAddr;
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end
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else begin
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pcRes <= pcIncr;
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end
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end
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$display("pc = %h",pcRes);
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end
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endmodule
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