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Update mips_cpu_regfile.v

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lb, lbu, lh, lhu now  select data according to address alignment
$0 is assigned to 0, may cause an error when written to, unknown.
This commit is contained in:
Aadi Desai 2020-12-06 17:42:23 +00:00
parent c5167645e7
commit d347475b64
1 changed files with 22 additions and 5 deletions
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27
rtl/mips_cpu_regfile.v
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@ -15,11 +15,12 @@ reg[31:0] memory [31:0]; //32 register slots, 32-bits wide
initial begin
integer i; //Initialise to zero by default
for (i = 0; i < 32; i++) begin
for (i = 1; i < 32; i++) begin
memory[i] = 0;
end
end
assign memory[0] = 32'h00000000;
assign regv0 = memory[2]; //assigning debug $v0 line to $2 of memory
always_comb begin
@ -31,16 +32,32 @@ always_ff @(negedge clk) begin
if (regwrite) begin
case (opcode)
6'b100000: begin //lb, load byte
memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]};
case (readdata1[1:0])
2'b00: memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]};
2'b01: memory[writereg] <= {{24{writedata[15]}}, writedata[15:8]};
2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]};
2'b11: memory[writereg] <= {{24{writedata[31]}}, writedata[31:24]};
endcase // readdata1[1:0]
end
6'b100100: begin //lbu, load byte unsigned
memory[writereg] <= {{24{1'b0}}, writedata[7:0]};
case (readdata1[1:0])
2'b00: memory[writereg] <= {{24{1'b0}}, writedata[7:0]};
2'b01: memory[writereg] <= {{24{1'b0}}, writedata[15:8]};
2'b10: memory[writereg] <= {{24{1'b0}}, writedata[23:16]};
2'b11: memory[writereg] <= {{24{1'b0}}, writedata[31:24]};
endcase // readdata1[1:0]
end
6'b100001: begin //lh, load half-word
memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]};
case (readdata1[1:0]) // must be half-word aligned, readdata1[0] = 0
2'b00: memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]};
2'b10: memory[writereg] <= {{16{writedata[31]}}, writedata[31:16]};
endcase // readdata1[1:0]
end
6'b100101: begin //lhu, load half-word unsigned
memory[writereg] <= {{16{1'b0}}, writedata[15:0]};
case (readdata1[1:0]) // must be half-word aligned, readdata1[0] = 0
2'b00: memory[writereg] <= {{16{1'b0}}, writedata[15:0]};
2'b10: memory[writereg] <= {{16{1'b0}}, writedata[31:16]};
endcase // readdata1[1:0]
end
6'b100010: begin //lwl, load word left
case (readdata1[1:0])