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Merge branch 'main' into bus_wrapper

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This commit is contained in:
Aadi Desai 2020-12-17 16:46:01 +00:00
parent 2be1978a36 cfebb403ba
commit cb29efd034
14 changed files with 65 additions and 114 deletions
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1
inputs/addu/addu-2.ref.txt Normal file
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@ -0,0 +1 @@
0

4
inputs/addu/addu-2.txt Normal file
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@ -0,0 +1,4 @@
3C041000
3C05F000
00000008
00851021

1
inputs/bgezal/bgezal-2.ref.txt Normal file
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@ -0,0 +1 @@
2

5
inputs/bgezal/bgezal-2.txt Normal file
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@ -0,0 +1,5 @@
3C04FFFF
04910004
03E00008
24420001
00000008

1
inputs/jr/jr-3.ref.txt Normal file
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@ -0,0 +1 @@
0

4
inputs/jr/jr-3.txt Normal file
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@ -0,0 +1,4 @@
3C05BFC0
34A50008
00A00008
00000008

44
reference/reference.txt
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@ -30,6 +30,20 @@ ADDU $2,$4,$5
register_v0 = 8
-Test not overflowing property
lui $4,$0,0x1000
lui $5,$0,0xF000
JR $0
ADDU $2,$4,$5
3C041000
3C05F000
00000008
00851021
register_v0 = 0
==AND Bitwise and==
LUI $5,0xCCCC
@ -126,6 +140,22 @@ JR $31
register_v0 = 2
-Testing whether it would link if branch fails
lui $4,0xFFFF
BGEZAL $4,4
JR $31
ADDIU $2,$2,1
JR $0
3C04FFFF
04910004
03E00008
24420001
00000008
register_v0 = 2
==BGTZ Branch on greater than zero==
ORI $4,$0,3
@ -363,6 +393,20 @@ ORI $2,$0,5
register_v0 = 5
-This broke testbench once due to log.txt weirdness
LUI $5,0xBFC0
ORI $5,$5,0x0008
JR $5
JR $0
3C05BFC0
34A50008
00A00008
00000008
register_v0 = 0
==LB Load byte==
ORI $4,$0,0x1001

3
rtl/mips_cpu_alu.v
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@ -135,7 +135,6 @@ end
SLL: begin
ALURes = B << shamt;
$display("ALURES SLL: %h", ALURes);
end
SLLV: begin
@ -169,7 +168,6 @@ end
end
LES: begin
$display("ALU A: %h B: %h", $signed(A), $signed(B));
if ($signed(A) < $signed(B)) begin
ALUCond = 1;
end
@ -248,7 +246,6 @@ end
end
DIVU: begin
$display("ALU A: %h B: %h", A, B);
temp_Lo = A / B;
temp_Hi = A % B;
end

26
rtl/mips_cpu_control.v
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@ -89,35 +89,28 @@ always @(*) begin
//CtrlRegDst logic
if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI))begin
CtrlRegDst = 2'd0; //Write address comes from rt
$display("CTRLREGDST: Rt");
end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin
CtrlRegDst = 2'd1; //Write address comes from rd
$display("CTRLREGDST: Rd");
end else if ((op == JAL) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin
CtrlRegDst = 2'd2; //const reg 31, for writing to the link register
$display("CTRLREGDST: Link");
end else begin CtrlRegDst = 1'bx; $display("xxxxxxxxxxxxxx");end//Not all instructions are encompassed so, added incase for debug purposes
end else begin CtrlRegDst = 1'bx; end//Not all instructions are encompassed so, added incase for debug purposes
//CtrlPC logic
if(ALUCond && ((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL)))))begin
CtrlPC = 2'd1; // Branches - Jumps relative to PC
end else if((op==J) || (op==JAL))begin
CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
$display("Jump PC Ctrl");
end else if((op==SPECIAL)&&((funct==JR) || (funct==JALR)))begin
CtrlPC = 2'd3; // Jumps using Register.
$display("Ctrl PC Jump Register");
end else begin CtrlPC = 2'd0; /*/$display("Ctrl PC No Jump/Branch");*/end // No jumps or branches, just increment to next word
end else begin CtrlPC = 2'd0; end // No jumps or branches, just increment to next word
//CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic where both are concerned. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled.
if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR))begin
CtrlMemRead = 1;//Memory is read enabled
CtrlMemtoReg = 3'd1;//write data port of regfile is fed from data memory
$display("Memory read enabled");
end else if ((op==ADDIU) || (op==ANDI) || (op==ORI) || (op==LUI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))))begin
CtrlMemRead = 0;//Memory is read disabled
CtrlMemtoReg = 3'd0;//write data port of regfile is fed from ALURes
$display("Memory read disabled");
end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin
CtrlMemtoReg = 3'd2;//write data port of regfile is fed from PC + 8
end else if ((op==SPECIAL)&&(funct == MFHI))begin
@ -127,11 +120,10 @@ always @(*) begin
end else if ((op==SPECIAL)&&(funct == JR))begin
CtrlMemRead = 0;//Read disabled during jump
end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
$display("OP: %d, Funct: %d", op, funct);
//CtrlALUOp Logic
if((op==ADDIU) || ((op==SPECIAL)&&(funct==ADDU)))begin
CtrlALUOp = 5'd0; //ADD from ALUOps
$display("ALU OP = 0 (ADDU/ADDIU)");
end else if((op==ANDI) || ((op==SPECIAL)&&(funct==AND)))begin
CtrlALUOp = 5'd4;//AND from ALUOps
end else if(op==BEQ) begin
@ -148,12 +140,10 @@ always @(*) begin
CtrlALUOp = 5'd18;//NEQ from ALUOps
end else if((op==SPECIAL)&&(funct==DIV))begin
CtrlALUOp = 5'd3;//DIV from ALUOps
$display("DIV CONTROL ALUOps");
end else if((op==SPECIAL)&&(funct==DIVU))begin
CtrlALUOp = 5'd23;//DIVU from ALUOps
end else if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin
CtrlALUOp = 5'd0;//ADD from ALUOps
$display("LB IN CONTROL");
end else if(op==LUI)begin
CtrlALUOp = 5'd7;//SLL from ALUOps
end else if((op==SPECIAL)&&((funct==MTHI)))begin
@ -168,31 +158,24 @@ always @(*) begin
CtrlALUOp = 5'd5;//OR from ALUOps
end else if((op==SPECIAL)&&(funct==SLL))begin
CtrlALUOp = 5'd7;//SLL from ALUOps
$display("ALU Op = 7 (SLL)");
end else if((op==SPECIAL)&&(funct==SLLV))begin
CtrlALUOp = 5'd8;//SLLV from ALUOps
$display("ALU Op = 9 (SLLV)");
end else if((op==SPECIAL)&&(funct==SRA))begin
CtrlALUOp = 5'd11;//SRA from ALUOps
$display("ALU Op = 11 (SRA)");
end else if((op==SPECIAL)&&(funct==SRAV))begin
CtrlALUOp = 5'd12;//SRAV from ALUOps
end else if((op==SPECIAL)&&(funct==SRL))begin
$display("ALU Op = 7 (SRL)");
CtrlALUOp = 5'd9;//SRL from ALUOps
end else if((op==SPECIAL)&&(funct==SRLV))begin
CtrlALUOp = 5'd10;//SRLV from ALUOps
end else if((op==SLTI) || ((op==SPECIAL)&&(funct==SLT)))begin
CtrlALUOp = 5'd20;//SLT from ALUOps
$display("ALU Op = 20 (SLT/SLTI)");
end else if((op==SLTIU) || ((op==SPECIAL)&&(funct==SLTU)))begin
CtrlALUOp = 5'd21;//SLTU from ALUOps
$display("ALU Op = 21 (SLTU/SLTIU)");
end else if((op==SPECIAL)&&(funct==SUBU))begin
CtrlALUOp = 5'd1;//SUB from ALUOps
end else if((op==XORI) || ((op==SPECIAL)&&(funct==XOR)))begin
CtrlALUOp = 5'd6;//XOR from ALUOps
$display("ALU Op = 6 (XOR)");
end else begin
CtrlALUOp = 5'bxxxxx;
end
@ -202,7 +185,6 @@ always @(*) begin
Ctrlshamt = Instr[10:6];// Shift amount piped in from the instruction
end else if(op == LUI)begin
Ctrlshamt = 5'd16;//Used specifically to implement LUI as the instruction itslef does not include shamt
$display("LUI SHIFTING");
end else begin Ctrlshamt = 5'bxxxxx;end
//CtrlMemWrite logic
@ -213,7 +195,6 @@ always @(*) begin
//CtrlSpcRegWriteEn logic
if((op==SPECIAL)&&((funct==MTHI) || (funct==MTLO) || (funct==MULT) || (funct==MULTU) || (funct==DIV) || (funct==DIVU)))begin
CtrlSpcRegWriteEn = 1;//Special register Hi and Lo are write enabled
$display("Temp being written");
end else begin CtrlSpcRegWriteEn = 0;end//default is 0 to ensure no accidental overwriting.
//CtrlALUSrc logic
@ -228,7 +209,6 @@ always @(*) begin
//CtrlRegWrite logic
if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
CtrlRegWrite = 1;//The Registers are Write Enabled
$display("OPcode mflo: %h", op);
end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
end
endmodule

1
rtl/mips_cpu_harvard.v
View file

@ -61,7 +61,6 @@ always @(*) begin
end
3'd2:begin
in_writedata = (out_pc_out + 32'd8);//Output from PC +8.
$display("LINKING-----------<: %h", in_writedata);
end
3'd3:begin
in_writedata = (out_ALUHi);

4
rtl/mips_cpu_regfile.v
View file

@ -29,7 +29,6 @@ always_ff @(negedge clk) begin
if (writereg == 5'b00000) begin
// skip writing if rd is $0
end else if (regwrite) begin
$display("%b", opcode);
case (opcode)
6'b100000: begin //lb, load byte
case (readdata1[1:0])
@ -38,8 +37,6 @@ always_ff @(negedge clk) begin
2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]};
2'b11: memory[writereg] <= {{24{writedata[31]}}, writedata[31:24]};
endcase // readdata1[1:0]
$display("writedata %h", writedata);
$display("memory writereg %h", memory[writereg]);
end
6'b100100: begin //lbu, load byte unsigned
case (readdata1[1:0])
@ -79,7 +76,6 @@ always_ff @(negedge clk) begin
end
default: begin
memory[writereg] <= writedata; //most instructions
$display("Write %d in regfile", writedata);
end
endcase // opcode
end

67
test/test_mips_cpu_custom.sh
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@ -1,67 +0,0 @@
#!/bin/bash
# arithmetic
./test/test_mips_cpu_harvard.sh rtl addu #Pass
./test/test_mips_cpu_harvard.sh rtl addiu #Pass
./test/test_mips_cpu_harvard.sh rtl subu #Pass
./test/test_mips_cpu_harvard.sh rtl and #Pass
./test/test_mips_cpu_harvard.sh rtl andi #Pass
./test/test_mips_cpu_harvard.sh rtl or #Pass
./test/test_mips_cpu_harvard.sh rtl ori #Pass
./test/test_mips_cpu_harvard.sh rtl xor #Pass
./test/test_mips_cpu_harvard.sh rtl xori #Pass
./test/test_mips_cpu_harvard.sh rtl div #Pass
./test/test_mips_cpu_harvard.sh rtl divu #pass
./test/test_mips_cpu_harvard.sh rtl mthi #Pass
./test/test_mips_cpu_harvard.sh rtl mtlo #Pass
./test/test_mips_cpu_harvard.sh rtl mult #Pass
./test/test_mips_cpu_harvard.sh rtl multu #Pass
# branches
./test/test_mips_cpu_harvard.sh rtl beq #Pass
./test/test_mips_cpu_harvard.sh rtl bgez #Pass
./test/test_mips_cpu_harvard.sh rtl bgezal #Pass
./test/test_mips_cpu_harvard.sh rtl bgtz #Pass
./test/test_mips_cpu_harvard.sh rtl blez #Pass
./test/test_mips_cpu_harvard.sh rtl bltz #Pass
./test/test_mips_cpu_harvard.sh rtl bltzal #Pass
./test/test_mips_cpu_harvard.sh rtl bne #Pass
# jumps
./test/test_mips_cpu_harvard.sh rtl j #Pass
./test/test_mips_cpu_harvard.sh rtl jalr #Pass
./test/test_mips_cpu_harvard.sh rtl jal #Pass
./test/test_mips_cpu_harvard.sh rtl jr #Pass
# shift
./test/test_mips_cpu_harvard.sh rtl sll #Pass
./test/test_mips_cpu_harvard.sh rtl srl #Pass
./test/test_mips_cpu_harvard.sh rtl sra #Pass
./test/test_mips_cpu_harvard.sh rtl srav #Pass
./test/test_mips_cpu_harvard.sh rtl sllv #Pass
./test/test_mips_cpu_harvard.sh rtl srlv #Pass
# load & store
./test/test_mips_cpu_harvard.sh rtl lw #Pass
./test/test_mips_cpu_harvard.sh rtl lb #Pass
./test/test_mips_cpu_harvard.sh rtl lbu #Pass
./test/test_mips_cpu_harvard.sh rtl lh #Pass
./test/test_mips_cpu_harvard.sh rtl lhu #Pass
./test/test_mips_cpu_harvard.sh rtl lui #Pass
./test/test_mips_cpu_harvard.sh rtl lwl #Pass
./test/test_mips_cpu_harvard.sh rtl lwr #Pass
./test/test_mips_cpu_harvard.sh rtl sw #Pass
#./test/test_mips_cpu_harvard.sh rtl sb #Once switched to bus
#./test/test_mips_cpu_harvard.sh rtl sh #Once switched to bus
# set on less than **Branch delay slots dont work on these...
./test/test_mips_cpu_harvard.sh rtl slti #Pass
./test/test_mips_cpu_harvard.sh rtl sltiu #Pass
./test/test_mips_cpu_harvard.sh rtl slt #Pass
./test/test_mips_cpu_harvard.sh rtl sltu #Pass

7
testbench/mips_cpu_harvard_tb.v
View file

@ -59,14 +59,7 @@ module mips_cpu_harvard_tb;
else $display("TB: CPU did not set active=1 after reset.");
while (active) begin
//$display("Clk: %d", clk);
@(posedge clk);
//$display("Register v0: %d", register_v0);
//$display("Reg File Write data: %d", cpuInst.in_writedata);
$display("Reg File Out Read data: %h", cpuInst.out_readdata1);
$display("Reg File opcode: %b", cpuInst.regfile.opcode);
//$display("ALU output: %h", cpuInst.out_ALURes);
//$display("ALU input B: %h", cpuInst.alu.B);
end
@(posedge clk);
$display("TB: CPU Halt; active=0");

7
testbench/mips_cpu_memory.v
View file

@ -56,16 +56,9 @@ module mips_cpu_memory(
//Synchronous write path
always_ff @(posedge clk) begin
//$display("Instruction: %h", instr_readdata);
//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
if (data_write) begin //cannot read and write to memory in the same cycle
if (instr_address != data_address) begin //cannot modify the instruction being read
data_memory[(data_address-32'h00001000)>>2] <= data_writedata;
$display("Store in memory");
$display(data_writedata);
end
for (integer k = 0; k<$size(data_memory); k++) begin
$display("byte +%h: %h", 32'h00001000+k*4, data_memory[k]);
end
end