From 6e626c5931077945548710d985b23c240de1b373 Mon Sep 17 00:00:00 2001
From: jl7719 <jl7719@imperial.ac.uk>
Date: Thu, 17 Dec 2020 10:32:52 +0000
Subject: [PATCH 1/9] Change location of the memory module from rtl to
 testbench

---
 test/test_mips_cpu_harvard.sh        | 4 ++--
 {rtl => testbench}/mips_cpu_memory.v | 0
 2 files changed, 2 insertions(+), 2 deletions(-)
 rename {rtl => testbench}/mips_cpu_memory.v (100%)

diff --git a/test/test_mips_cpu_harvard.sh b/test/test_mips_cpu_harvard.sh
index 19cb6b7..e5cd348 100755
--- a/test/test_mips_cpu_harvard.sh
+++ b/test/test_mips_cpu_harvard.sh
@@ -25,7 +25,7 @@ then
                 -s mips_cpu_harvard_tb \
                 -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.txt\" \
                 -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \
-                -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \
+                -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_memory.v\
                 ${SRC} 2> /dev/null
             ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt;             # log file for debugging (contains $display)
             echo "$(tail -1 ./inputs/${DIR}/${TESTCASE}.log.txt)" > ./inputs/${DIR}/${TESTCASE}.out.txt;      # register v0 output to compare with reference
@@ -46,7 +46,7 @@ else
         -s mips_cpu_harvard_tb \
         -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \
         -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \
-        -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \
+        -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_memory.v\
         ${SRC} 2> /dev/null
         ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt;             # log file for debugging (contains $display)
         echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt;      # register v0 output to compare with reference
diff --git a/rtl/mips_cpu_memory.v b/testbench/mips_cpu_memory.v
similarity index 100%
rename from rtl/mips_cpu_memory.v
rename to testbench/mips_cpu_memory.v

From 15dfce09c9497ec9417d6694946172e4fc187419 Mon Sep 17 00:00:00 2001
From: theexecutor13 <yanhoipuk@yahoo.com>
Date: Thu, 17 Dec 2020 19:44:23 +0800
Subject: [PATCH 2/9] Update reference.txt

---
 reference.txt | 285 +++++++++++++++++++++++---------------------------
 1 file changed, 132 insertions(+), 153 deletions(-)

diff --git a/reference.txt b/reference.txt
index 493a0f9..ebd0fdd 100644
--- a/reference.txt
+++ b/reference.txt
@@ -7,12 +7,12 @@ Reference Output
 ==ADDIU Add immediate unsigned (no overflow)==
 
 ORI $4,$0,0xA
-ADDIU $2,$4,20
 JR $0
+ADDIU $2,$4,20
 
 3404000a
-24820014
 00000008
+24820014
 
 register_v0 = 30
 
@@ -20,13 +20,13 @@ register_v0 = 30
 
 ORI $4,$0,3
 ORI $5,$0,5
-ADDU $2,$4,$5
 JR $0
+ADDU $2,$4,$5
 
 34040003
 34050005
-00851021
 00000008
+00851021
 
 register_v0 = 8
 
@@ -36,31 +36,31 @@ LUI $5,0xCCCC
 ORI $5,$5,0xCCCC
 LUI $4,0xAAAA 
 ORI $4,$4,0xAAAA
-AND  $2,$4,$5
 JR $0
+AND  $2,$4,$5
 
 3c05cccc 
 34A5cccc
 3c04aaaa
 3484aaaa
-00851024
 00000008
+00851024
 
-register_v0 = 0x88888888
+register_v0 = 0x88888888 / 2290649224
 
 ==ANDI Bitwise and immediate==
 
 LUI $4,0xAAAA 
 ORI $4,$0,0xAAAA
-ANDI $2,$4,0xCCCC
 JR $0
+ANDI $2,$4,0xCCCC
 
 3c04aaaa
 3404aaaa
-3082cccc
 00000008
+3082cccc
 
-register_v0 = 0x00008888
+register_v0 = 0x00008888 / 34952
 
 ==BEQ	Branch on equal==
 
@@ -104,22 +104,6 @@ JR $0
 
 register_v0 = 1
 
-ORI $4,$0,3
-BGEZ $4,3
-NOP
-ADDIU $2,$2,1
-NOP
-ADDIU $2,$2,5
-JR $0
-
-34040003
-04810003
-00000000
-24420001
-00000000
-24420005
-00000008
-
 ==BGEZAL Branch on non-negative (>=0) and link==
 
 ORI $4,$0,3
@@ -284,7 +268,7 @@ JR $0
 00851021
 00000008
 
-register_v0 = 0x40000000
+register_v0 = 0x40000000 / 1073741824
 
 ==J	Jump==
 
@@ -307,7 +291,7 @@ register_v0 = 1
 ==JALR	Jump and link register==
 
 LUI $5,0xBFC0
-ORI $5,$0,0x001C
+ORI $5,$5,0x001C
 JALR $4,$5
 NOP
 ADDIU $2,$2,1
@@ -317,7 +301,7 @@ ORI $2,$0,1
 JR $4
 
 3C05BCF0
-3405001C
+34A5001C
 00A02009
 00000000
 24420001
@@ -371,78 +355,78 @@ register_v0 = 10
 
 ==LB	Load byte==
 
-ORI $4,$0,0x1003
-LB  $2,3($4)
+ORI $4,$0,0x1001
 JR $0
+LB  $2,5($4)
+
+-Instruction Hex
+
+34041001
+00000008
+80820005
+
+-Memory Hex
+
+00000000
+008A0000
+00000000
+00000000
+
+register_v0 = 0xFFFFFF8A / 4294967178
+
+==LBU	Load byte unsigned==
+
+ORI $4,$0,0x1002
+JR $0
+LBU  $2,4($4)
+
+-Instruction Hex
+
+34041002
+00000008
+90820004
+
+-Memory Hex
+
+00000000
+008A0000
+00000000
+00000000
+
+register_v0 = 0x0000008A / 138
+
+==LH	Load half-word==
+
+ORI $4,$0,0x1000
+JR $0
+LH  $2,4($4)
+
+-Instruction Hex
+
+34041003
+00000008
+84820004
+
+-Memory Hex
+
+00000000
+00008123
+00000000
+00000000
+
+register_v0 = 0xFFFF8123 / 4294934819
+
+==LHU	Load half-word unsigned==
+
+ORI $4,$0,0x1000
+JR $0
+LHU $2,4($4)
 
 -Instruction Hex
 
 34041000
-80820006
 00000008
-
--Memory Hex
-
-00000000
-008A0000
-00000000
-00000000
-
-register_v0 = 0xFFFFFF8A
-
-==LBU	Load byte unsigned==
-
-ORI $4,$0,0x1003
-LBU  $2,3($4)
-JR $0
-
--Instruction Hex
-
-34041003
-90820003
-00000008
-
--Memory Hex
-
-00000000
-008A0000
-00000000
-00000000
-
-register_v0 = 0x0000008A
-
-==LH	Load half-word==
-
-ORI $4,$0,0x1003
-LH  $2,4($4)
-JR $0
-
--Instruction Hex
-
-34041003
-84820004
-00000008
-
--Memory Hex
-
-00000000
-00008123
-00000000
-00000000
-
-register_v0 = 0xFFFF8123
-
-==LHU	Load half-word unsigned==
-
-ORI $4,$0,0x1003
-LHU $2,4($4)
-JR $0
-
--Instruction Hex
-
-34041003
 94820004
-00000008
 
 -Memory Hex
 
@@ -451,7 +435,7 @@ JR $0
 00000000
 00000000
 
-register_v0 = 0x00008123
+register_v0 = 0x00008123 / 33059
 
 ==LUI	Load upper immediate==
 
@@ -463,19 +447,19 @@ JR $0
 34425678
 00000008
 
-register_v0 = 0x12345678
+register_v0 = 0x12345678 / 305419896
 
 ==LW	Load word==
 
 ORI $4,$0,0x1002
-LW  $2, 2($4)
 JR $0
+LW  $2, 2($4)
 
 -Instruction Hex
 
 34041002
-8C820002
 00000008
+8C820002
 
 -Memory Hex
 
@@ -484,21 +468,21 @@ JR $0
 00000000
 00000000
 
-register_v0 = 0x12345678
+register_v0 = 0x12345678 / 305419896
 
 ==LWL	Load word left==
 
 ORI $4,$0,0x1001
 ORI $2,$0,0x5678
-LWL  $2,3($4)
 JR $0
+LWL  $2,3($4)
 
 -Instruction Hex
 
 34041001
 34025678
-88820003
 00000008
+88820003
 
 -Memory Hex
 
@@ -507,21 +491,21 @@ AAAA1234
 00000000
 00000000
 
-register_v0 = 0x12345678
+register_v0 = 0x12345678 / 305419896
 
 ==LWR	Load word right==
 
 LUI $2,0x1234
 ORI $4,$0,0x1002
-LWR $2,3($4)
 JR $0
+LWR $2,3($4)
 
 -Instruction Hex
 
 3C021234
 34041002
-98820003
 00000008
+98820003
 
 -Memory Hex
 
@@ -530,7 +514,7 @@ JR $0
 00000000
 00000000
 
-register_v0 = 0x12345678
+register_v0 = 0x12345678 / 305419896
 
 ==MTHI	Move to HI==
 
@@ -596,33 +580,27 @@ register_v0 = 12
 
 ori $4, $0, 5
 ori $5, $0, 3
-or $2, $4, $5
 jr $0
+or $2, $4, $5
 
 34040005
 34050003
-00851025
 00000008
+00851025
 
 register_v0 = 7
 
-
 ==ORI	Bitwise or immediate==
 
-ori $2, $0, 3
-ori $2, $2, 5
-jr $0
-
-34020003
-00000008
-34420005
-
-register_v0 = 7
-
 ori $4, $0, 0xFFFF
 ori $5, $0, 0x1234
-or $2, $4, $5
 jr $0
+or $2, $4, $5
+
+3404FFFF
+34051234
+00851025
+00000008
 
 register_v0 = 65535
 
@@ -669,12 +647,13 @@ register_v0 = 0x00005678
 ==SLL	Shift left logical==
 
 ori $4,$0,3
-sll $2,$4,2
 jr $0
+sll $2,$4,2
+
 
 34040003
-00041080
 00000008
+00041080
 
 register_v0 = 12
 
@@ -682,13 +661,13 @@ register_v0 = 12
 
 ori $4,$0,2
 ori $5,$0,3
-sllv $2,$5,$4
 jr $0
+sllv $2,$5,$4
 
 34040002
 34050003
-00851004
 00000008
+00851004
 
 register_v0 = 12
 
@@ -696,37 +675,37 @@ register_v0 = 12
 
 ORI $4 $zero 0xFFFF
 ORI $5 $zero 0x000B
-SLT $2 $4 $5
 jr $0
+SLT $2 $4 $5
 
 3404FFFF
 3405000B
-0085102A
 00000008
+0085102A
 
 register_v0 = 0
 
 ==SLTI	Set on less than immediate (signed)==
 
 ori $4, $0, 10
-slti $2, $4, 9
 jr $0
+slti $2, $4, 9
 
 3404000a
-28820009
 00000008
+28820009
 
 register_v0 = 0
 
 ==SLTIU	Set on less than immediate unsigned==
 
 ori $4, $0, 10
-sltiu $2, $4, 9
 jr $0
+sltiu $2, $4, 9
 
 3404000a
-2c820009
 00000008
+2c820009
 
 register_v0 = 0
 
@@ -734,53 +713,51 @@ register_v0 = 0
 
 ori $4, $0, 10
 ori $5, $0, 9
-sltu $2, $4, $5
 jr $0
+sltu $2, $4, $5
 
 3404000a
 34050009
-0085102b
 00000008
+0085102b
 
 register_v0 = 0
 
 ==SRA	Shift right arithmetic==
 
 lui $5 $0,0xF000
+jr $0  
 srav $2,$5,2
-jr $0    
-
+  
 3C05F000
-00051083
 00000008
+00051083
 
-register_v0 = 0xFC000000
+register_v0 = 0xFC000000 / 4227858432
 
 ==SRAV	Shift right arithmetic variable==
 
 ori $4,$0,2
 lui $5, 0xF000
+jr $0  
 srav $2,$5,$4
-jr $0    
 
-F000000 -> FC000000
-
-34040004
+34040002
 3C05F000
-00851007
 00000008
+00851007
 
-register_v0 = 0xFC000000
+register_v0 = 0xFC000000 / 4227858432
 
 ==SRL	Shift right logical==
 
 ori $4,$0,16
-srl $2,$4,2
 jr $0
+srl $2,$4,2
 
 34040010
-00041082
 00000008
+00041082
 
 register_v0 = 4
 
@@ -788,13 +765,13 @@ register_v0 = 4
 
 ori $4,$0,2
 ori $5,$0,16
-srlv $2,$5,$4
 jr $0
+srlv $2,$5,$4
 
 34040002
 34050010
-00851006
 00000008
+00851006
 
 register_v0 = 4
 
@@ -802,13 +779,13 @@ register_v0 = 4
 
 ori $4,$0,5
 ori $5,$0,3
-subu $2,$4,$5
 jr $0
+subu $2,$4,$5
 
 34040005
 34050003
-00851023
 00000008
+00851023
 
 register_v0 = 2
 
@@ -826,7 +803,9 @@ ACA40004
 8CA20004
 00000008
 
-register_v0 = 0x0000FFFF
+register_v0 = 0x0000FFFF / 65535
+
+-Negative Offset
 
 ori $4, $0, 0xFFFF     
 ori $5, $0, 0x1008    
@@ -840,30 +819,30 @@ ACA4FFFC
 8CA2FFFC
 00000008
 
-register_v0 = 0x0000FFFF
+register_v0 = 0x0000FFFF / 65535
 
 ==XOR	Bitwise exclusive or==
 
 ori $4, $0, 5
 ori $5, $0, 2
-xor $2, $4, $5
 jr $0
+xor $2, $4, $5
 
 34040005
 34050002
-00851026
 00000008
+00851026
 
 register_v0 = 7
 
 ==XORI	Bitwise exclusive or immediate==
 
 ori $4,$0,5
-xori $2,$4,0x000F
 jr $0
+xori $2,$4,0x000F
 
 34040005
-3882000F
 00000008
+3882000F
 
 register_v0 = 10

From 4ab4809a8a6806fee6904635b199c5616d4acf45 Mon Sep 17 00:00:00 2001
From: theexecutor13 <yanhoipuk@yahoo.com>
Date: Thu, 17 Dec 2020 11:47:13 +0000
Subject: [PATCH 3/9] restructuring

---
 reference.txt                                 |  848 ----------
 .../Instructions.xlsx                         |  Bin
 mips-isa.pdf => reference/mips-isa.pdf        |  Bin
 reference/reference.txt                       | 1412 ++++++++++-------
 structure.png => reference/structure.png      |  Bin
 5 files changed, 848 insertions(+), 1412 deletions(-)
 delete mode 100644 reference.txt
 rename Instructions.xlsx => reference/Instructions.xlsx (100%)
 rename mips-isa.pdf => reference/mips-isa.pdf (100%)
 rename structure.png => reference/structure.png (100%)

diff --git a/reference.txt b/reference.txt
deleted file mode 100644
index ebd0fdd..0000000
--- a/reference.txt
+++ /dev/null
@@ -1,848 +0,0 @@
-== Instruction ==
-Assembly code
-Hex code
-Reference Output
-================
-
-==ADDIU Add immediate unsigned (no overflow)==
-
-ORI $4,$0,0xA
-JR $0
-ADDIU $2,$4,20
-
-3404000a
-00000008
-24820014
-
-register_v0 = 30
-
-== ADDU Add unsigned (no overflow) ==
-
-ORI $4,$0,3
-ORI $5,$0,5
-JR $0
-ADDU $2,$4,$5
-
-34040003
-34050005
-00000008
-00851021
-
-register_v0 = 8
-
-==AND Bitwise and==
-
-LUI $5,0xCCCC
-ORI $5,$5,0xCCCC
-LUI $4,0xAAAA 
-ORI $4,$4,0xAAAA
-JR $0
-AND  $2,$4,$5
-
-3c05cccc 
-34A5cccc
-3c04aaaa
-3484aaaa
-00000008
-00851024
-
-register_v0 = 0x88888888 / 2290649224
-
-==ANDI Bitwise and immediate==
-
-LUI $4,0xAAAA 
-ORI $4,$0,0xAAAA
-JR $0
-ANDI $2,$4,0xCCCC
-
-3c04aaaa
-3404aaaa
-00000008
-3082cccc
-
-register_v0 = 0x00008888 / 34952
-
-==BEQ	Branch on equal==
-
-ORI $4,$0,5
-ORI $5,$0,5
-BEQ $4,$5,3
-NOP 
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-34040005
-34050005
-10850003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==BGEZ Branch on greater than or equal to zero==
-
-ORI $4,$0,3
-BGEZ $4,3
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-34040003
-04810003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==BGEZAL Branch on non-negative (>=0) and link==
-
-ORI $4,$0,3
-BGEZAL $4,4
-NOP
-ADDIU $2,$2,1
-JR $0
-NOP
-ORI $2,$0,1
-JR $31
-
-34040003
-04910004
-00000000
-24420001
-00000008
-00000000
-34020001
-03E00008
-
-register_v0 = 2
-
-==BGTZ Branch on greater than zero==
-
-ORI $4,$0,3
-BGTZ $4,3
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-34040003
-1C800003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==BLEZ Branch on less than or equal to zero==
-
-LUI $4,0xFFFF
-BLEZ $4,3
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-3C05FFFF
-18800003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==BLTZ Branch on less than zero==
-
-LUI $4,0xFFFF 
-BLTZ $4,3
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-3C04FFFF
-04800003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==BLTZAL	Branch on less than zero and link==
-
-LUI $4,0xFFFF 
-BLTZAL $4,4
-NOP
-ADDIU $2,$2,1
-JR $0
-NOP
-ORI $2,$0,1
-JR $31
-
-3C05FFFF
-04900004
-00000000
-24420001
-00000008
-00000000
-34020001
-03E00008
-
-register_v0 = 2
-
-==BNE	Branch on not equal==
-
-ORI $4,$0,3
-ORI $5,$0,5
-BNE $4,$5,3
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-34040003
-34040005
-14850003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==DIV	Divide== //May need other testcases for -ve/+ve, -ve/-ve
-
-ORI $4,$0,3
-ORI $5,$0,9
-DIV  $5,$4
-MFHI $4
-MFLO $5
-ADDU $2,$4,$5
-JR $0
-
-34040003
-34050009
-00A4001A
-00002010
-00002812
-00851021
-00000008
-
-register_v0 = 3
-
-==DIVU	Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve
-
-LUI $4,0x8000
-ORI $5,$0,2
-DIVU  $4,$5
-MFHI $4
-MFLO $5 
-ADDU $2,$4,$5
-JR $0
-
-3C048000
-34050002
-0085001B
-00002010
-00002812
-00851021
-00000008
-
-register_v0 = 0x40000000 / 1073741824
-
-==J	Jump==
-
-J 4
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-08000004
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==JALR	Jump and link register==
-
-LUI $5,0xBFC0
-ORI $5,$5,0x001C
-JALR $4,$5
-NOP
-ADDIU $2,$2,1
-JR $0
-NOP
-ORI $2,$0,1
-JR $4
-
-3C05BCF0
-34A5001C
-00A02009
-00000000
-24420001
-00000008
-00000000
-34020001
-00800008
-
-register_v0 = 2
-
-==JAL	Jump and link==
-
-JAL 5
-NOP
-ADDIU $2,$2,1
-JR $0
-NOP
-ORI $2,$0,1
-JR $31
-
-0C000005
-00000000
-24420001
-00000008
-00000000
-34020001
-03E00008
-
-register_v0 = 2
-
-==JR	Jump register==
-
-LUI $5,0xBFC0  
-ORI $5,$5,0x0014
-JR $5  
-NOP
-JR $0
-NOP
-ORI $2,$0,0xA
-JR $0
-
-3C05BFC0
-34A50014
-00A00008
-00000000
-00000008
-3402000A
-00000008
-
-register_v0 = 10
-
-==LB	Load byte==
-
-ORI $4,$0,0x1001
-JR $0
-LB  $2,5($4)
-
--Instruction Hex
-
-34041001
-00000008
-80820005
-
--Memory Hex
-
-00000000
-008A0000
-00000000
-00000000
-
-register_v0 = 0xFFFFFF8A / 4294967178
-
-==LBU	Load byte unsigned==
-
-ORI $4,$0,0x1002
-JR $0
-LBU  $2,4($4)
-
--Instruction Hex
-
-34041002
-00000008
-90820004
-
--Memory Hex
-
-00000000
-008A0000
-00000000
-00000000
-
-register_v0 = 0x0000008A / 138
-
-==LH	Load half-word==
-
-ORI $4,$0,0x1000
-JR $0
-LH  $2,4($4)
-
--Instruction Hex
-
-34041003
-00000008
-84820004
-
--Memory Hex
-
-00000000
-00008123
-00000000
-00000000
-
-register_v0 = 0xFFFF8123 / 4294934819
-
-==LHU	Load half-word unsigned==
-
-ORI $4,$0,0x1000
-JR $0
-LHU $2,4($4)
-
--Instruction Hex
-
-34041000
-00000008
-94820004
-
--Memory Hex
-
-00000000
-00008123
-00000000
-00000000
-
-register_v0 = 0x00008123 / 33059
-
-==LUI	Load upper immediate==
-
-LUI $2,0x1234
-ORI $2,$2,0x5678
-JR $0
-
-3C021234
-34425678
-00000008
-
-register_v0 = 0x12345678 / 305419896
-
-==LW	Load word==
-
-ORI $4,$0,0x1002
-JR $0
-LW  $2, 2($4)
-
--Instruction Hex
-
-34041002
-00000008
-8C820002
-
--Memory Hex
-
-00000000
-12345678
-00000000
-00000000
-
-register_v0 = 0x12345678 / 305419896
-
-==LWL	Load word left==
-
-ORI $4,$0,0x1001
-ORI $2,$0,0x5678
-JR $0
-LWL  $2,3($4)
-
--Instruction Hex
-
-34041001
-34025678
-00000008
-88820003
-
--Memory Hex
-
-00000000
-AAAA1234
-00000000
-00000000
-
-register_v0 = 0x12345678 / 305419896
-
-==LWR	Load word right==
-
-LUI $2,0x1234
-ORI $4,$0,0x1002
-JR $0
-LWR $2,3($4)
-
--Instruction Hex
-
-3C021234
-34041002
-00000008
-98820003
-
--Memory Hex
-
-00000000
-5678AAAA
-00000000
-00000000
-
-register_v0 = 0x12345678 / 305419896
-
-==MTHI	Move to HI==
-
-ori $4, $0, 5
-mthi $4
-mfhi $2
-jr $0
-
-34040005
-00800011
-00001010
-00000008
-
-register_v0 = 5
-
-==MTLO	Move to LO==
-
-ori $4, $0, 5
-mtlo $4
-mflo $2
-jr $0
-
-34040005
-00800013
-00001012
-00000008
-
-register_v0 = 5
-
-==MULT	Multiply==
-
-ori $4, $0, 4
-ori $5, $0, 3
-mult $4, $5
-mflo $2
-jr $0
-
-34040004
-34050003
-00850018
-00001012
-00000008
-
-register_v0 = 12
-
-==MULTU	Multiply unsigned==
-
-ori $4, $0, 4
-ori $5, $0, 3
-multu $4, $5
-mflo $2
-jr $0
-
-34040004
-34050003
-00850019
-00001012
-00000008
-
-register_v0 = 12
-
-==OR	Bitwise or==
-
-ori $4, $0, 5
-ori $5, $0, 3
-jr $0
-or $2, $4, $5
-
-34040005
-34050003
-00000008
-00851025
-
-register_v0 = 7
-
-==ORI	Bitwise or immediate==
-
-ori $4, $0, 0xFFFF
-ori $5, $0, 0x1234
-jr $0
-or $2, $4, $5
-
-3404FFFF
-34051234
-00851025
-00000008
-
-register_v0 = 65535
-
-==SB	Store byte==
-
-lui $4, 0x1234
-ori $4, $0, 0x5678
-lui $5, 0xBFC0
-ori $5, $0, 0x001C
-sb $4, 0($5)
-lb $2, 0($5)
-jr $0
-
-3C041234
-34045678
-3C05BFC0
-3405001C
-A0A40000
-80A20000
-00000008
-
-register_v0 = 0x00000078
-
-==SH	Store half-word==
-
-lui $4, 0x1234
-ori $4, $0, 0x5678
-lui $5, 0xBFC0
-ori $5, $0, 0x001C
-sh $4, 0($5)
-lh $2, 0($5)
-jr $0
-
-3C041234
-34045678
-3C05BFC0
-3405001C
-A4A40000
-84A40000
-00000008
-
-register_v0 = 0x00005678
-
-==SLL	Shift left logical==
-
-ori $4,$0,3
-jr $0
-sll $2,$4,2
-
-
-34040003
-00000008
-00041080
-
-register_v0 = 12
-
-==SLLV	Shift left logical variable==
-
-ori $4,$0,2
-ori $5,$0,3
-jr $0
-sllv $2,$5,$4
-
-34040002
-34050003
-00000008
-00851004
-
-register_v0 = 12
-
-==SLT	Set on less than (signed)==
-
-ORI $4 $zero 0xFFFF
-ORI $5 $zero 0x000B
-jr $0
-SLT $2 $4 $5
-
-3404FFFF
-3405000B
-00000008
-0085102A
-
-register_v0 = 0
-
-==SLTI	Set on less than immediate (signed)==
-
-ori $4, $0, 10
-jr $0
-slti $2, $4, 9
-
-3404000a
-00000008
-28820009
-
-register_v0 = 0
-
-==SLTIU	Set on less than immediate unsigned==
-
-ori $4, $0, 10
-jr $0
-sltiu $2, $4, 9
-
-3404000a
-00000008
-2c820009
-
-register_v0 = 0
-
-==SLTU	Set on less than unsigned==
-
-ori $4, $0, 10
-ori $5, $0, 9
-jr $0
-sltu $2, $4, $5
-
-3404000a
-34050009
-00000008
-0085102b
-
-register_v0 = 0
-
-==SRA	Shift right arithmetic==
-
-lui $5 $0,0xF000
-jr $0  
-srav $2,$5,2
-  
-3C05F000
-00000008
-00051083
-
-register_v0 = 0xFC000000 / 4227858432
-
-==SRAV	Shift right arithmetic variable==
-
-ori $4,$0,2
-lui $5, 0xF000
-jr $0  
-srav $2,$5,$4
-
-34040002
-3C05F000
-00000008
-00851007
-
-register_v0 = 0xFC000000 / 4227858432
-
-==SRL	Shift right logical==
-
-ori $4,$0,16
-jr $0
-srl $2,$4,2
-
-34040010
-00000008
-00041082
-
-register_v0 = 4
-
-==SRLV	Shift right logical variable==
-
-ori $4,$0,2
-ori $5,$0,16
-jr $0
-srlv $2,$5,$4
-
-34040002
-34050010
-00000008
-00851006
-
-register_v0 = 4
-
-==SUBU	Subtract unsigned==
-
-ori $4,$0,5
-ori $5,$0,3
-jr $0
-subu $2,$4,$5
-
-34040005
-34050003
-00000008
-00851023
-
-register_v0 = 2
-
-==SW	Store word==
-
-ori $4, $0, 0xFFFF     
-ori $5, $0, 0x1008    
-sw $4, 4($5)      
-lw $2, 4($5)                    
-jr $0               
-
-3404FFFF
-34051008
-ACA40004
-8CA20004
-00000008
-
-register_v0 = 0x0000FFFF / 65535
-
--Negative Offset
-
-ori $4, $0, 0xFFFF     
-ori $5, $0, 0x1008    
-sw $4, -4($5)      
-lw $2, -4($5)                    
-jr $0               
-
-3404FFFF
-34051008
-ACA4FFFC
-8CA2FFFC
-00000008
-
-register_v0 = 0x0000FFFF / 65535
-
-==XOR	Bitwise exclusive or==
-
-ori $4, $0, 5
-ori $5, $0, 2
-jr $0
-xor $2, $4, $5
-
-34040005
-34050002
-00000008
-00851026
-
-register_v0 = 7
-
-==XORI	Bitwise exclusive or immediate==
-
-ori $4,$0,5
-jr $0
-xori $2,$4,0x000F
-
-34040005
-00000008
-3882000F
-
-register_v0 = 10
diff --git a/Instructions.xlsx b/reference/Instructions.xlsx
similarity index 100%
rename from Instructions.xlsx
rename to reference/Instructions.xlsx
diff --git a/mips-isa.pdf b/reference/mips-isa.pdf
similarity index 100%
rename from mips-isa.pdf
rename to reference/mips-isa.pdf
diff --git a/reference/reference.txt b/reference/reference.txt
index 8583183..ebd0fdd 100644
--- a/reference/reference.txt
+++ b/reference/reference.txt
@@ -1,564 +1,848 @@
-== Instruction ==
-C code
-Assembly code
-Hex code
-Reference Output
-================
-
-ADDIU Add immediate unsigned (no overflow) 
-
-== ADDU Add unsigned (no overflow) ==
-
-int main(void) {
-    int a = 3 + 5;
-}
-
-ORI $4,$0,3
-ORI $5,$0,5
-ADDU $2,$4,$5
-JR $0
-
-34040003
-34050005
-00851021
-00000008
-
-register_v0 = 8
-
-==AND Bitwise and==
-
-ORI $5,$0,0xCCCC
-LUI $5,0xCCCC 
-ORI $4,$0,0xAAAA
-LUI $4,0xAAAA  
-AND  $2,$4,$5
-JR $0
-
-3405cccc
-3c05cccc
-3404aaaa
-3c04aaaa
-00851024
-00000008
-
-register_v0 = 0x88888888
-
-==ANDI Bitwise and immediate==
-
-ORI $4,$0,0xAAAA
-LUI $4,0xAAAA  
-ANDI $2,$4,0xCCCC
-JR $0
-
-3404aaaa
-3c04aaaa
-3082cccc
-00000008
-
-register_v0 = 0x00008888
-
-==BEQ	Branch on equal==
-
-ORI $4,$0,5
-ORI $5,$0,5
-BEQ $4,$5,3
-NOP 
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-34040005
-34050005
-10850003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==BGEZ Branch on greater than or equal to zero==
-
-ORI $4,$0,3
-BGEZ $4,3
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-34040003
-04810003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==BGEZAL Branch on non-negative (>=0) and link==
-
-ORI $4,$0,3
-BGEZAL $4,4
-NOP
-ADDIU $2,$2,1
-JR $0
-NOP
-ORI $2,$0,1
-JR $31
-
-34040003
-04910004
-00000000
-24420001
-00000008
-00000000
-34020001
-03E00008
-
-register_v0 = 2
-
-==BGTZ Branch on greater than zero==
-
-ORI $4,$0,3
-BGTZ $4,3
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-34040003
-1C800003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==BLEZ Branch on less than or equal to zero==
-
-LUI $4,0xFFFF
-BLEZ $4,3
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-3C05FFFF
-18800003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==BLTZ Branch on less than zero==
-
-LUI $4,0xFFFF 
-BLTZ $4,3
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-3C05FFFF
-04800003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==BLTZAL	Branch on less than zero and link==
-
-LUI $4,0xFFFF 
-BLTZAL $4,4
-NOP
-ADDIU $2,$2,1
-JR $0
-NOP
-ORI $2,$0,1
-JR $31
-
-3C05FFFF
-04900004
-00000000
-24420001
-00000008
-00000000
-34020001
-03E00008
-
-register_v0 = 2
-
-==BNE	Branch on not equal==
-
-ORI $4,$0,3
-ORI $5,$0,5
-BNE $4,$5,3
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-34040003
-34040005
-14850003
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==DIV	Divide== //May need other testcases for -ve/+ve, -ve/-ve
-
-ORI $4,$0,3
-ORI $5,$0,9
-DIV  $5,$4
-MFHI $4
-MFLO $5
-ADDU $2,$4,$5
-JR $0
-
-34040003
-34050009
-00A4001A
-00002010
-00002812
-00851021
-00000008
-
-register_v0 = 3
-
-==DIVU	Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve
-
-LUI $4,0x8000 
-ORI $5,$0,2
-DIVU  $4,$5
-MFHI $4
-MFLO $5
-ADDU $2,$4,$5
-JR $0
-
-34048000
-34050002
-0085001B
-00002010
-00002812
-00851021
-00000008
-
-register_v0 = 0x40000000
-
-==J	Jump==
-
-J 4
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-08000004
-00000000
-00000008
-00000000
-34020001
-00000008
-
-register_v0 = 1
-
-==JALR	Jump and link register==
-
-ORI $5,$0,0x001C
-LUI $5,0xBFC0
-JALR $4,$5
-NOP
-ADDIU $2,$2,1
-JR $0
-NOP
-ORI $2,$0,1
-JR $4
-
-3405001C
-3C05BCF0
-00A02009
-00000000
-24420001
-00000008
-00000000
-34020001
-00800008
-
-register_v0 = 2
-
-==JAL	Jump and link==
-
-JAL 5
-NOP
-ADDIU $2,$2,1
-JR $0
-NOP
-ORI $2,$0,1
-JR $31
-
-0C000005
-00000000
-24420001
-00000008
-00000000
-34020001
-03E00008
-
-register_v0 = 2
-
-==JR	Jump register==
-
-ORI $5,$0,0x0014
-LUI $5,0xBFC0  
-JR $5  
-NOP
-JR $0
-NOP
-ORI $2,$0,1
-JR $0
-
-34050014
-3C05BCF0
-00A00008
-00000000
-00000008
-34020001
-00000008
-
-register_v0 = 1
-
-==LB	Load byte==
-
-ORI $4,$0,0x1003
-LB  $2,3($4)
-JR $0
-
--Instruction Hex
-
-34041003
-80820003
-00000008
-
--Memory Hex
-
-00000000
-008A0000
-00000000
-00000000
-
-register_v0 = 0xFFFFFF8A
-
-==LBU	Load byte unsigned==
-
-ORI $4,$0,0x1003
-LBU  $2,3($4)
-JR $0
-
--Instruction Hex
-
-34041003
-90820003
-00000008
-
--Memory Hex
-
-00000000
-008A0000
-00000000
-00000000
-
-register_v0 = 0x0000008A
-
-==LH	Load half-word==
-
-ORI $4,$0,0x1003
-LH  $2,4($4)
-JR $0
-
--Instruction Hex
-
-34041003
-84820004
-00000008
-
--Memory Hex
-
-00000000
-00008123
-00000000
-00000000
-
-register_v0 = 0xFFFF8123
-
-==LHU	Load half-word unsigned==
-
-ORI $4,$0,0x1003
-LHU $2,4($4)
-JR $0
-
--Instruction Hex
-
-34041003
-94820004
-00000008
-
--Memory Hex
-
-00000000
-00008123
-00000000
-00000000
-
-register_v0 = 0x00008123
-
-==LUI	Load upper immediate==
-
-ORI $2,$0,0x5678
-LUI $2,0x1234
-JR $0
-
-34045678
-3C021234
-00000008
-
-register_v0 = 0x12345678
-
-==LW	Load word==
-
-ORI $4,$0,0x1002
-LW  $2, 2($4)
-JR $0
-
--Instruction Hex
-
-34041002
-8C820002
-00000008
-
--Memory Hex
-
-00000000
-12345678
-00000000
-00000000
-
-register_v0 = 0x12345678
-
-==LWL	Load word left==
-
-ORI $4,$0,0x1003
-ORI $2,$0,0x5678
-LWL  $2,3($4)
-JR $0
-
--Instruction Hex
-
-34041003
-34025678
-88820003
-00000008
-
--Memory Hex
-
-00000000
-AAAA1234
-00000000
-00000000
-
-register_v0 = 0x12345678
-
-==LWR	Load word right==
-
-ORI $4,$0,0x1003
-LUI $2,0x1234
-LWR $2,2($4)
-JR $0
-
--Instruction Hex
-
-34041003
-3C021234
-98820002
-00000008
-
--Memory Hex
-
-00000000
-5678AAAA
-00000000
-00000000
-
-register_v0 = 0x12345678
-
-// DIVU Divide unsigned
-
-// DIV Divide
-
-//MFHI Move from Hi 
-
-//MFLO Move from lo 
-
-//MTHI	Move to HI
-
-//MTLO	Move to LO
-
-//MULT	Multiply**
-
-//MULTU	Multiply unsigned**
-
-//OR	Bitwise or
-
-//ORI	Bitwise or immediate
-
-//SB	Store byte
-
-//SH	Store half-word**
-
-//SLL	Shift left logical
-
-//SLLV	Shift left logical variable 
-
-//SLT	Set on less than (signed)
-
-//SLTI	Set on less than immediate (signed)
-
-//SLTIU	Set on less than immediate unsigned
-
-//SLTU	Set on less than unsigned
-
-//SRA	Shift right arithmetic
-
-//SRAV	Shift right arithmetic
-
-//SRL	Shift right logical
-
-//SRLV	Shift right logical variable
-
-//SUBU	Subtract unsigned
-
-//SW	Store word
-
-//XOR	Bitwise exclusive or
-
-//XORI	Bitwise exclusive or immediate
+== Instruction ==
+Assembly code
+Hex code
+Reference Output
+================
+
+==ADDIU Add immediate unsigned (no overflow)==
+
+ORI $4,$0,0xA
+JR $0
+ADDIU $2,$4,20
+
+3404000a
+00000008
+24820014
+
+register_v0 = 30
+
+== ADDU Add unsigned (no overflow) ==
+
+ORI $4,$0,3
+ORI $5,$0,5
+JR $0
+ADDU $2,$4,$5
+
+34040003
+34050005
+00000008
+00851021
+
+register_v0 = 8
+
+==AND Bitwise and==
+
+LUI $5,0xCCCC
+ORI $5,$5,0xCCCC
+LUI $4,0xAAAA 
+ORI $4,$4,0xAAAA
+JR $0
+AND  $2,$4,$5
+
+3c05cccc 
+34A5cccc
+3c04aaaa
+3484aaaa
+00000008
+00851024
+
+register_v0 = 0x88888888 / 2290649224
+
+==ANDI Bitwise and immediate==
+
+LUI $4,0xAAAA 
+ORI $4,$0,0xAAAA
+JR $0
+ANDI $2,$4,0xCCCC
+
+3c04aaaa
+3404aaaa
+00000008
+3082cccc
+
+register_v0 = 0x00008888 / 34952
+
+==BEQ	Branch on equal==
+
+ORI $4,$0,5
+ORI $5,$0,5
+BEQ $4,$5,3
+NOP 
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+34040005
+34050005
+10850003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==BGEZ Branch on greater than or equal to zero==
+
+ORI $4,$0,3
+BGEZ $4,3
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+34040003
+04810003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==BGEZAL Branch on non-negative (>=0) and link==
+
+ORI $4,$0,3
+BGEZAL $4,4
+NOP
+ADDIU $2,$2,1
+JR $0
+NOP
+ORI $2,$0,1
+JR $31
+
+34040003
+04910004
+00000000
+24420001
+00000008
+00000000
+34020001
+03E00008
+
+register_v0 = 2
+
+==BGTZ Branch on greater than zero==
+
+ORI $4,$0,3
+BGTZ $4,3
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+34040003
+1C800003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==BLEZ Branch on less than or equal to zero==
+
+LUI $4,0xFFFF
+BLEZ $4,3
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+3C05FFFF
+18800003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==BLTZ Branch on less than zero==
+
+LUI $4,0xFFFF 
+BLTZ $4,3
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+3C04FFFF
+04800003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==BLTZAL	Branch on less than zero and link==
+
+LUI $4,0xFFFF 
+BLTZAL $4,4
+NOP
+ADDIU $2,$2,1
+JR $0
+NOP
+ORI $2,$0,1
+JR $31
+
+3C05FFFF
+04900004
+00000000
+24420001
+00000008
+00000000
+34020001
+03E00008
+
+register_v0 = 2
+
+==BNE	Branch on not equal==
+
+ORI $4,$0,3
+ORI $5,$0,5
+BNE $4,$5,3
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+34040003
+34040005
+14850003
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==DIV	Divide== //May need other testcases for -ve/+ve, -ve/-ve
+
+ORI $4,$0,3
+ORI $5,$0,9
+DIV  $5,$4
+MFHI $4
+MFLO $5
+ADDU $2,$4,$5
+JR $0
+
+34040003
+34050009
+00A4001A
+00002010
+00002812
+00851021
+00000008
+
+register_v0 = 3
+
+==DIVU	Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve
+
+LUI $4,0x8000
+ORI $5,$0,2
+DIVU  $4,$5
+MFHI $4
+MFLO $5 
+ADDU $2,$4,$5
+JR $0
+
+3C048000
+34050002
+0085001B
+00002010
+00002812
+00851021
+00000008
+
+register_v0 = 0x40000000 / 1073741824
+
+==J	Jump==
+
+J 4
+NOP
+JR $0
+NOP
+ORI $2,$0,1
+JR $0
+
+08000004
+00000000
+00000008
+00000000
+34020001
+00000008
+
+register_v0 = 1
+
+==JALR	Jump and link register==
+
+LUI $5,0xBFC0
+ORI $5,$5,0x001C
+JALR $4,$5
+NOP
+ADDIU $2,$2,1
+JR $0
+NOP
+ORI $2,$0,1
+JR $4
+
+3C05BCF0
+34A5001C
+00A02009
+00000000
+24420001
+00000008
+00000000
+34020001
+00800008
+
+register_v0 = 2
+
+==JAL	Jump and link==
+
+JAL 5
+NOP
+ADDIU $2,$2,1
+JR $0
+NOP
+ORI $2,$0,1
+JR $31
+
+0C000005
+00000000
+24420001
+00000008
+00000000
+34020001
+03E00008
+
+register_v0 = 2
+
+==JR	Jump register==
+
+LUI $5,0xBFC0  
+ORI $5,$5,0x0014
+JR $5  
+NOP
+JR $0
+NOP
+ORI $2,$0,0xA
+JR $0
+
+3C05BFC0
+34A50014
+00A00008
+00000000
+00000008
+3402000A
+00000008
+
+register_v0 = 10
+
+==LB	Load byte==
+
+ORI $4,$0,0x1001
+JR $0
+LB  $2,5($4)
+
+-Instruction Hex
+
+34041001
+00000008
+80820005
+
+-Memory Hex
+
+00000000
+008A0000
+00000000
+00000000
+
+register_v0 = 0xFFFFFF8A / 4294967178
+
+==LBU	Load byte unsigned==
+
+ORI $4,$0,0x1002
+JR $0
+LBU  $2,4($4)
+
+-Instruction Hex
+
+34041002
+00000008
+90820004
+
+-Memory Hex
+
+00000000
+008A0000
+00000000
+00000000
+
+register_v0 = 0x0000008A / 138
+
+==LH	Load half-word==
+
+ORI $4,$0,0x1000
+JR $0
+LH  $2,4($4)
+
+-Instruction Hex
+
+34041003
+00000008
+84820004
+
+-Memory Hex
+
+00000000
+00008123
+00000000
+00000000
+
+register_v0 = 0xFFFF8123 / 4294934819
+
+==LHU	Load half-word unsigned==
+
+ORI $4,$0,0x1000
+JR $0
+LHU $2,4($4)
+
+-Instruction Hex
+
+34041000
+00000008
+94820004
+
+-Memory Hex
+
+00000000
+00008123
+00000000
+00000000
+
+register_v0 = 0x00008123 / 33059
+
+==LUI	Load upper immediate==
+
+LUI $2,0x1234
+ORI $2,$2,0x5678
+JR $0
+
+3C021234
+34425678
+00000008
+
+register_v0 = 0x12345678 / 305419896
+
+==LW	Load word==
+
+ORI $4,$0,0x1002
+JR $0
+LW  $2, 2($4)
+
+-Instruction Hex
+
+34041002
+00000008
+8C820002
+
+-Memory Hex
+
+00000000
+12345678
+00000000
+00000000
+
+register_v0 = 0x12345678 / 305419896
+
+==LWL	Load word left==
+
+ORI $4,$0,0x1001
+ORI $2,$0,0x5678
+JR $0
+LWL  $2,3($4)
+
+-Instruction Hex
+
+34041001
+34025678
+00000008
+88820003
+
+-Memory Hex
+
+00000000
+AAAA1234
+00000000
+00000000
+
+register_v0 = 0x12345678 / 305419896
+
+==LWR	Load word right==
+
+LUI $2,0x1234
+ORI $4,$0,0x1002
+JR $0
+LWR $2,3($4)
+
+-Instruction Hex
+
+3C021234
+34041002
+00000008
+98820003
+
+-Memory Hex
+
+00000000
+5678AAAA
+00000000
+00000000
+
+register_v0 = 0x12345678 / 305419896
+
+==MTHI	Move to HI==
+
+ori $4, $0, 5
+mthi $4
+mfhi $2
+jr $0
+
+34040005
+00800011
+00001010
+00000008
+
+register_v0 = 5
+
+==MTLO	Move to LO==
+
+ori $4, $0, 5
+mtlo $4
+mflo $2
+jr $0
+
+34040005
+00800013
+00001012
+00000008
+
+register_v0 = 5
+
+==MULT	Multiply==
+
+ori $4, $0, 4
+ori $5, $0, 3
+mult $4, $5
+mflo $2
+jr $0
+
+34040004
+34050003
+00850018
+00001012
+00000008
+
+register_v0 = 12
+
+==MULTU	Multiply unsigned==
+
+ori $4, $0, 4
+ori $5, $0, 3
+multu $4, $5
+mflo $2
+jr $0
+
+34040004
+34050003
+00850019
+00001012
+00000008
+
+register_v0 = 12
+
+==OR	Bitwise or==
+
+ori $4, $0, 5
+ori $5, $0, 3
+jr $0
+or $2, $4, $5
+
+34040005
+34050003
+00000008
+00851025
+
+register_v0 = 7
+
+==ORI	Bitwise or immediate==
+
+ori $4, $0, 0xFFFF
+ori $5, $0, 0x1234
+jr $0
+or $2, $4, $5
+
+3404FFFF
+34051234
+00851025
+00000008
+
+register_v0 = 65535
+
+==SB	Store byte==
+
+lui $4, 0x1234
+ori $4, $0, 0x5678
+lui $5, 0xBFC0
+ori $5, $0, 0x001C
+sb $4, 0($5)
+lb $2, 0($5)
+jr $0
+
+3C041234
+34045678
+3C05BFC0
+3405001C
+A0A40000
+80A20000
+00000008
+
+register_v0 = 0x00000078
+
+==SH	Store half-word==
+
+lui $4, 0x1234
+ori $4, $0, 0x5678
+lui $5, 0xBFC0
+ori $5, $0, 0x001C
+sh $4, 0($5)
+lh $2, 0($5)
+jr $0
+
+3C041234
+34045678
+3C05BFC0
+3405001C
+A4A40000
+84A40000
+00000008
+
+register_v0 = 0x00005678
+
+==SLL	Shift left logical==
+
+ori $4,$0,3
+jr $0
+sll $2,$4,2
+
+
+34040003
+00000008
+00041080
+
+register_v0 = 12
+
+==SLLV	Shift left logical variable==
+
+ori $4,$0,2
+ori $5,$0,3
+jr $0
+sllv $2,$5,$4
+
+34040002
+34050003
+00000008
+00851004
+
+register_v0 = 12
+
+==SLT	Set on less than (signed)==
+
+ORI $4 $zero 0xFFFF
+ORI $5 $zero 0x000B
+jr $0
+SLT $2 $4 $5
+
+3404FFFF
+3405000B
+00000008
+0085102A
+
+register_v0 = 0
+
+==SLTI	Set on less than immediate (signed)==
+
+ori $4, $0, 10
+jr $0
+slti $2, $4, 9
+
+3404000a
+00000008
+28820009
+
+register_v0 = 0
+
+==SLTIU	Set on less than immediate unsigned==
+
+ori $4, $0, 10
+jr $0
+sltiu $2, $4, 9
+
+3404000a
+00000008
+2c820009
+
+register_v0 = 0
+
+==SLTU	Set on less than unsigned==
+
+ori $4, $0, 10
+ori $5, $0, 9
+jr $0
+sltu $2, $4, $5
+
+3404000a
+34050009
+00000008
+0085102b
+
+register_v0 = 0
+
+==SRA	Shift right arithmetic==
+
+lui $5 $0,0xF000
+jr $0  
+srav $2,$5,2
+  
+3C05F000
+00000008
+00051083
+
+register_v0 = 0xFC000000 / 4227858432
+
+==SRAV	Shift right arithmetic variable==
+
+ori $4,$0,2
+lui $5, 0xF000
+jr $0  
+srav $2,$5,$4
+
+34040002
+3C05F000
+00000008
+00851007
+
+register_v0 = 0xFC000000 / 4227858432
+
+==SRL	Shift right logical==
+
+ori $4,$0,16
+jr $0
+srl $2,$4,2
+
+34040010
+00000008
+00041082
+
+register_v0 = 4
+
+==SRLV	Shift right logical variable==
+
+ori $4,$0,2
+ori $5,$0,16
+jr $0
+srlv $2,$5,$4
+
+34040002
+34050010
+00000008
+00851006
+
+register_v0 = 4
+
+==SUBU	Subtract unsigned==
+
+ori $4,$0,5
+ori $5,$0,3
+jr $0
+subu $2,$4,$5
+
+34040005
+34050003
+00000008
+00851023
+
+register_v0 = 2
+
+==SW	Store word==
+
+ori $4, $0, 0xFFFF     
+ori $5, $0, 0x1008    
+sw $4, 4($5)      
+lw $2, 4($5)                    
+jr $0               
+
+3404FFFF
+34051008
+ACA40004
+8CA20004
+00000008
+
+register_v0 = 0x0000FFFF / 65535
+
+-Negative Offset
+
+ori $4, $0, 0xFFFF     
+ori $5, $0, 0x1008    
+sw $4, -4($5)      
+lw $2, -4($5)                    
+jr $0               
+
+3404FFFF
+34051008
+ACA4FFFC
+8CA2FFFC
+00000008
+
+register_v0 = 0x0000FFFF / 65535
+
+==XOR	Bitwise exclusive or==
+
+ori $4, $0, 5
+ori $5, $0, 2
+jr $0
+xor $2, $4, $5
+
+34040005
+34050002
+00000008
+00851026
+
+register_v0 = 7
+
+==XORI	Bitwise exclusive or immediate==
+
+ori $4,$0,5
+jr $0
+xori $2,$4,0x000F
+
+34040005
+00000008
+3882000F
+
+register_v0 = 10
diff --git a/structure.png b/reference/structure.png
similarity index 100%
rename from structure.png
rename to reference/structure.png

From ab13c84ef5d3e1c83d3c566b3099086f473b72a9 Mon Sep 17 00:00:00 2001
From: theexecutor13 <yanhoipuk@yahoo.com>
Date: Thu, 17 Dec 2020 12:03:30 +0000
Subject: [PATCH 4/9] testing branch delay slot

---
 inputs/addiu/addiu-1.txt     | 2 +-
 inputs/addiu/addiu-2.ref.txt | 1 -
 inputs/addiu/addiu-2.txt     | 2 --
 inputs/addu/addu-1.txt       | 2 +-
 inputs/and/and-1.txt         | 2 +-
 inputs/andi/andi-1.txt       | 2 +-
 inputs/lb/lb-1.txt           | 2 +-
 inputs/lbu/lbu-1.txt         | 2 +-
 inputs/lh/lh-1.txt           | 2 +-
 inputs/lhu/lhu-1.txt         | 2 +-
 inputs/lw/lw-1.txt           | 2 +-
 inputs/lwl/lwl-1.txt         | 2 +-
 inputs/lwr/lwr-1.txt         | 2 +-
 inputs/or/or-1.txt           | 2 +-
 inputs/ori/ori-1.ref.txt     | 2 +-
 inputs/ori/ori-1.txt         | 6 ++++--
 inputs/ori/ori-2.ref.txt     | 1 -
 inputs/ori/ori-2.txt         | 4 ----
 inputs/sll/sll-1.txt         | 2 +-
 inputs/sllv/sllv-1.txt       | 2 +-
 inputs/slt/slt-1.txt         | 4 ++--
 inputs/slt/slt-2.ref.txt     | 1 -
 inputs/slt/slt-2.txt         | 4 ----
 inputs/sra/sra-1.txt         | 3 ++-
 inputs/srav/srav-1.txt       | 3 ++-
 inputs/srl/srl-1.txt         | 2 +-
 inputs/srlv/srlv-1.txt       | 2 +-
 inputs/subu/subu-1.txt       | 2 +-
 inputs/xori/xori-1.txt       | 4 +---
 29 files changed, 29 insertions(+), 40 deletions(-)
 delete mode 100644 inputs/addiu/addiu-2.ref.txt
 delete mode 100644 inputs/addiu/addiu-2.txt
 delete mode 100644 inputs/ori/ori-2.ref.txt
 delete mode 100644 inputs/ori/ori-2.txt
 delete mode 100644 inputs/slt/slt-2.ref.txt
 delete mode 100644 inputs/slt/slt-2.txt

diff --git a/inputs/addiu/addiu-1.txt b/inputs/addiu/addiu-1.txt
index 62290ae..7401d7b 100644
--- a/inputs/addiu/addiu-1.txt
+++ b/inputs/addiu/addiu-1.txt
@@ -1,3 +1,3 @@
 3404000a
+00000008
 24820014
-00000008
\ No newline at end of file
diff --git a/inputs/addiu/addiu-2.ref.txt b/inputs/addiu/addiu-2.ref.txt
deleted file mode 100644
index 9a03714..0000000
--- a/inputs/addiu/addiu-2.ref.txt
+++ /dev/null
@@ -1 +0,0 @@
-10
\ No newline at end of file
diff --git a/inputs/addiu/addiu-2.txt b/inputs/addiu/addiu-2.txt
deleted file mode 100644
index 664859c..0000000
--- a/inputs/addiu/addiu-2.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-2442000A
-00000008
\ No newline at end of file
diff --git a/inputs/addu/addu-1.txt b/inputs/addu/addu-1.txt
index 1c079df..5d98337 100644
--- a/inputs/addu/addu-1.txt
+++ b/inputs/addu/addu-1.txt
@@ -1,4 +1,4 @@
 34040003
 34050005
+00000008
 00851021
-00000008
\ No newline at end of file
diff --git a/inputs/and/and-1.txt b/inputs/and/and-1.txt
index 7a287c6..f50bee1 100644
--- a/inputs/and/and-1.txt
+++ b/inputs/and/and-1.txt
@@ -2,5 +2,5 @@
 34A5cccc
 3c04aaaa
 3484aaaa
+00000008
 00851024
-00000008
\ No newline at end of file
diff --git a/inputs/andi/andi-1.txt b/inputs/andi/andi-1.txt
index ccc9aa9..a927a1b 100644
--- a/inputs/andi/andi-1.txt
+++ b/inputs/andi/andi-1.txt
@@ -1,4 +1,4 @@
 3c04aaaa
 3404aaaa
+00000008
 3082cccc
-00000008
\ No newline at end of file
diff --git a/inputs/lb/lb-1.txt b/inputs/lb/lb-1.txt
index 43aa99a..940d1c7 100644
--- a/inputs/lb/lb-1.txt
+++ b/inputs/lb/lb-1.txt
@@ -1,3 +1,3 @@
 34041001
+00000008
 80820005
-00000008
\ No newline at end of file
diff --git a/inputs/lbu/lbu-1.txt b/inputs/lbu/lbu-1.txt
index 14f9e84..0c0c283 100644
--- a/inputs/lbu/lbu-1.txt
+++ b/inputs/lbu/lbu-1.txt
@@ -1,3 +1,3 @@
 34041002
+00000008
 90820004
-00000008
\ No newline at end of file
diff --git a/inputs/lh/lh-1.txt b/inputs/lh/lh-1.txt
index aa12925..f3c6ebd 100644
--- a/inputs/lh/lh-1.txt
+++ b/inputs/lh/lh-1.txt
@@ -1,3 +1,3 @@
 34041000
+00000008
 84820004
-00000008
\ No newline at end of file
diff --git a/inputs/lhu/lhu-1.txt b/inputs/lhu/lhu-1.txt
index d8bc6f1..f185691 100644
--- a/inputs/lhu/lhu-1.txt
+++ b/inputs/lhu/lhu-1.txt
@@ -1,3 +1,3 @@
 34041000
+00000008
 94820004
-00000008
\ No newline at end of file
diff --git a/inputs/lw/lw-1.txt b/inputs/lw/lw-1.txt
index 7c6a2ee..702ed31 100644
--- a/inputs/lw/lw-1.txt
+++ b/inputs/lw/lw-1.txt
@@ -1,3 +1,3 @@
 34041002
+00000008
 8C820002
-00000008
\ No newline at end of file
diff --git a/inputs/lwl/lwl-1.txt b/inputs/lwl/lwl-1.txt
index c682e96..5ba291d 100644
--- a/inputs/lwl/lwl-1.txt
+++ b/inputs/lwl/lwl-1.txt
@@ -1,4 +1,4 @@
 34041001
 34025678
+00000008
 88820003
-00000008
\ No newline at end of file
diff --git a/inputs/lwr/lwr-1.txt b/inputs/lwr/lwr-1.txt
index 633db20..7f2641f 100644
--- a/inputs/lwr/lwr-1.txt
+++ b/inputs/lwr/lwr-1.txt
@@ -1,4 +1,4 @@
 3C021234
 34041002
+00000008
 98820003
-00000008
\ No newline at end of file
diff --git a/inputs/or/or-1.txt b/inputs/or/or-1.txt
index 25df299..7d9b029 100644
--- a/inputs/or/or-1.txt
+++ b/inputs/or/or-1.txt
@@ -1,4 +1,4 @@
 34040005
 34050003
+00000008
 00851025
-00000008
\ No newline at end of file
diff --git a/inputs/ori/ori-1.ref.txt b/inputs/ori/ori-1.ref.txt
index c793025..35ff949 100644
--- a/inputs/ori/ori-1.ref.txt
+++ b/inputs/ori/ori-1.ref.txt
@@ -1 +1 @@
-7
\ No newline at end of file
+65535
\ No newline at end of file
diff --git a/inputs/ori/ori-1.txt b/inputs/ori/ori-1.txt
index b41478b..35a84da 100644
--- a/inputs/ori/ori-1.txt
+++ b/inputs/ori/ori-1.txt
@@ -1,3 +1,5 @@
-34020003
-34420005
+3404FFFF
+34051234
 00000008
+00851025
+
diff --git a/inputs/ori/ori-2.ref.txt b/inputs/ori/ori-2.ref.txt
deleted file mode 100644
index 35ff949..0000000
--- a/inputs/ori/ori-2.ref.txt
+++ /dev/null
@@ -1 +0,0 @@
-65535
\ No newline at end of file
diff --git a/inputs/ori/ori-2.txt b/inputs/ori/ori-2.txt
deleted file mode 100644
index b13206a..0000000
--- a/inputs/ori/ori-2.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-3404FFFF
-34052134
-00851025
-00000008
diff --git a/inputs/sll/sll-1.txt b/inputs/sll/sll-1.txt
index e03a5d2..8956883 100644
--- a/inputs/sll/sll-1.txt
+++ b/inputs/sll/sll-1.txt
@@ -1,3 +1,3 @@
 34040003
+00000008
 00041080
-00000008
\ No newline at end of file
diff --git a/inputs/sllv/sllv-1.txt b/inputs/sllv/sllv-1.txt
index d733281..5eaf2c8 100644
--- a/inputs/sllv/sllv-1.txt
+++ b/inputs/sllv/sllv-1.txt
@@ -1,4 +1,4 @@
 34040002
 34050003
+00000008
 00851004
-00000008
\ No newline at end of file
diff --git a/inputs/slt/slt-1.txt b/inputs/slt/slt-1.txt
index 2d14014..d58bdf7 100644
--- a/inputs/slt/slt-1.txt
+++ b/inputs/slt/slt-1.txt
@@ -1,4 +1,4 @@
-3404000F
+3404FFFF
 3405000B
 00000008
-0085102A
\ No newline at end of file
+0085102A
diff --git a/inputs/slt/slt-2.ref.txt b/inputs/slt/slt-2.ref.txt
deleted file mode 100644
index c227083..0000000
--- a/inputs/slt/slt-2.ref.txt
+++ /dev/null
@@ -1 +0,0 @@
-0
\ No newline at end of file
diff --git a/inputs/slt/slt-2.txt b/inputs/slt/slt-2.txt
deleted file mode 100644
index 013d035..0000000
--- a/inputs/slt/slt-2.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-3404FFFF
-3405000B
-0085102A
-00000008
\ No newline at end of file
diff --git a/inputs/sra/sra-1.txt b/inputs/sra/sra-1.txt
index 1cb5924..d7817c1 100644
--- a/inputs/sra/sra-1.txt
+++ b/inputs/sra/sra-1.txt
@@ -1,3 +1,4 @@
 3C05F000
-00051083
 00000008
+00051083
+
diff --git a/inputs/srav/srav-1.txt b/inputs/srav/srav-1.txt
index 8d6dad2..681d41b 100644
--- a/inputs/srav/srav-1.txt
+++ b/inputs/srav/srav-1.txt
@@ -1,4 +1,5 @@
 34040002
 3C05F000
-00851007
 00000008
+00851007
+
diff --git a/inputs/srl/srl-1.txt b/inputs/srl/srl-1.txt
index 581aa82..4ac3949 100644
--- a/inputs/srl/srl-1.txt
+++ b/inputs/srl/srl-1.txt
@@ -1,3 +1,3 @@
 34040010
+00000008
 00041082
-00000008
\ No newline at end of file
diff --git a/inputs/srlv/srlv-1.txt b/inputs/srlv/srlv-1.txt
index ae99941..ebd01e3 100644
--- a/inputs/srlv/srlv-1.txt
+++ b/inputs/srlv/srlv-1.txt
@@ -1,4 +1,4 @@
 34040002
 34050010
+00000008
 00851006
-00000008
\ No newline at end of file
diff --git a/inputs/subu/subu-1.txt b/inputs/subu/subu-1.txt
index 7c8a7eb..d4590d9 100644
--- a/inputs/subu/subu-1.txt
+++ b/inputs/subu/subu-1.txt
@@ -1,4 +1,4 @@
 34040005
 34050003
+00000008
 00851023
-00000008
\ No newline at end of file
diff --git a/inputs/xori/xori-1.txt b/inputs/xori/xori-1.txt
index 4fe9205..c85639a 100644
--- a/inputs/xori/xori-1.txt
+++ b/inputs/xori/xori-1.txt
@@ -1,5 +1,3 @@
 34040005
-3882000F
 00000008
-00000000
-00000000
\ No newline at end of file
+3882000F

From 7fcc2486cb86e7026f3d95eac2d0f863d3f853fd Mon Sep 17 00:00:00 2001
From: theexecutor13 <yanhoipuk@yahoo.com>
Date: Thu, 17 Dec 2020 13:37:00 +0000
Subject: [PATCH 5/9] cleanup

---
 inputs/beq/beq-2.ref.txt   | 1 -
 inputs/beq/beq-2.txt       | 8 --------
 inputs/bgez/bgez-2.ref.txt | 1 -
 inputs/bgez/bgez-2.txt     | 7 -------
 4 files changed, 17 deletions(-)
 delete mode 100644 inputs/beq/beq-2.ref.txt
 delete mode 100644 inputs/beq/beq-2.txt
 delete mode 100644 inputs/bgez/bgez-2.ref.txt
 delete mode 100644 inputs/bgez/bgez-2.txt

diff --git a/inputs/beq/beq-2.ref.txt b/inputs/beq/beq-2.ref.txt
deleted file mode 100644
index 60d3b2f..0000000
--- a/inputs/beq/beq-2.ref.txt
+++ /dev/null
@@ -1 +0,0 @@
-15
diff --git a/inputs/beq/beq-2.txt b/inputs/beq/beq-2.txt
deleted file mode 100644
index 07e24de..0000000
--- a/inputs/beq/beq-2.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-34040005
-34050005
-10850003
-34020005
-00000008
-00000000
-2442000A
-00000008
\ No newline at end of file
diff --git a/inputs/bgez/bgez-2.ref.txt b/inputs/bgez/bgez-2.ref.txt
deleted file mode 100644
index 7813681..0000000
--- a/inputs/bgez/bgez-2.ref.txt
+++ /dev/null
@@ -1 +0,0 @@
-5
\ No newline at end of file
diff --git a/inputs/bgez/bgez-2.txt b/inputs/bgez/bgez-2.txt
deleted file mode 100644
index 13d6d41..0000000
--- a/inputs/bgez/bgez-2.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-34040003
-04810003
-00000000
-24420001
-00000000
-24420005
-00000008
\ No newline at end of file

From 0bdbb63f4956a7bb8130d59acc64e425530225f3 Mon Sep 17 00:00:00 2001
From: theexecutor13 <yanhoipuk@yahoo.com>
Date: Thu, 17 Dec 2020 21:37:17 +0800
Subject: [PATCH 6/9] Update reference.txt

---
 reference/reference.txt | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/reference/reference.txt b/reference/reference.txt
index ebd0fdd..0639738 100644
--- a/reference/reference.txt
+++ b/reference/reference.txt
@@ -353,6 +353,16 @@ JR $0
 
 register_v0 = 10
 
+-Branch Delay slot test
+
+JR $0
+ORI $2,$0,5
+
+00000008
+34020005
+
+register_v0 = 5
+
 ==LB	Load byte==
 
 ORI $4,$0,0x1001

From 6c400f3567bd31a97fa7accd646dc64e90086b85 Mon Sep 17 00:00:00 2001
From: theexecutor13 <yanhoipuk@yahoo.com>
Date: Thu, 17 Dec 2020 14:31:33 +0000
Subject: [PATCH 7/9] uploading log.txt weirdness testcase

---
 inputs/addu/addu-2.ref.txt     |  1 +
 inputs/addu/addu-2.txt         |  4 ++++
 inputs/bgezal/bgezal-2.ref.txt |  1 +
 inputs/bgezal/bgezal-2.txt     |  5 ++++
 inputs/jr/jr-3.ref.txt         |  1 +
 inputs/jr/jr-3.txt             |  4 ++++
 reference/reference.txt        | 44 ++++++++++++++++++++++++++++++++++
 7 files changed, 60 insertions(+)
 create mode 100644 inputs/addu/addu-2.ref.txt
 create mode 100644 inputs/addu/addu-2.txt
 create mode 100644 inputs/bgezal/bgezal-2.ref.txt
 create mode 100644 inputs/bgezal/bgezal-2.txt
 create mode 100644 inputs/jr/jr-3.ref.txt
 create mode 100644 inputs/jr/jr-3.txt

diff --git a/inputs/addu/addu-2.ref.txt b/inputs/addu/addu-2.ref.txt
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/inputs/addu/addu-2.ref.txt
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/inputs/addu/addu-2.txt b/inputs/addu/addu-2.txt
new file mode 100644
index 0000000..d6bfc13
--- /dev/null
+++ b/inputs/addu/addu-2.txt
@@ -0,0 +1,4 @@
+3C041000
+3C05F000
+00000008
+00851021
diff --git a/inputs/bgezal/bgezal-2.ref.txt b/inputs/bgezal/bgezal-2.ref.txt
new file mode 100644
index 0000000..d8263ee
--- /dev/null
+++ b/inputs/bgezal/bgezal-2.ref.txt
@@ -0,0 +1 @@
+2
\ No newline at end of file
diff --git a/inputs/bgezal/bgezal-2.txt b/inputs/bgezal/bgezal-2.txt
new file mode 100644
index 0000000..dc238df
--- /dev/null
+++ b/inputs/bgezal/bgezal-2.txt
@@ -0,0 +1,5 @@
+3C04FFFF
+04910004
+03E00008
+24420001
+00000008
diff --git a/inputs/jr/jr-3.ref.txt b/inputs/jr/jr-3.ref.txt
new file mode 100644
index 0000000..c227083
--- /dev/null
+++ b/inputs/jr/jr-3.ref.txt
@@ -0,0 +1 @@
+0
\ No newline at end of file
diff --git a/inputs/jr/jr-3.txt b/inputs/jr/jr-3.txt
new file mode 100644
index 0000000..92b32e4
--- /dev/null
+++ b/inputs/jr/jr-3.txt
@@ -0,0 +1,4 @@
+3C05BFC0
+34A50008
+00A00008
+00000008
diff --git a/reference/reference.txt b/reference/reference.txt
index 0639738..8d016c9 100644
--- a/reference/reference.txt
+++ b/reference/reference.txt
@@ -30,6 +30,20 @@ ADDU $2,$4,$5
 
 register_v0 = 8
 
+-Test not overflowing property
+
+lui $4,$0,0x1000
+lui $5,$0,0xF000
+JR $0
+ADDU $2,$4,$5
+
+3C041000
+3C05F000
+00000008
+00851021
+
+register_v0 = 0
+
 ==AND Bitwise and==
 
 LUI $5,0xCCCC
@@ -126,6 +140,22 @@ JR $31
 
 register_v0 = 2
 
+-Testing whether it would link if branch fails
+
+lui $4,0xFFFF
+BGEZAL $4,4
+JR $31
+ADDIU $2,$2,1
+JR $0
+
+3C04FFFF
+04910004
+03E00008
+24420001
+00000008
+
+register_v0 = 2
+
 ==BGTZ Branch on greater than zero==
 
 ORI $4,$0,3
@@ -363,6 +393,20 @@ ORI $2,$0,5
 
 register_v0 = 5
 
+-This broke testbench once due to log.txt weirdness
+
+LUI $5,0xBFC0  
+ORI $5,$5,0x0008
+JR $5  
+JR $0
+
+3C05BFC0
+34A50008
+00A00008
+00000008
+
+register_v0 = 0
+
 ==LB	Load byte==
 
 ORI $4,$0,0x1001

From 2d9cca262ddd9949eebbb1a1f21373e2de31c29b Mon Sep 17 00:00:00 2001
From: jl7719 <jl7719@imperial.ac.uk>
Date: Thu, 17 Dec 2020 14:51:08 +0000
Subject: [PATCH 8/9] Fix display appearing at the end of log file

---
 rtl/mips_cpu_control.v          |  6 +--
 test/test_mips_cpu_custom.sh    | 67 ---------------------------------
 testbench/mips_cpu_harvard_tb.v |  4 +-
 3 files changed, 5 insertions(+), 72 deletions(-)
 delete mode 100755 test/test_mips_cpu_custom.sh

diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v
index 5ce988b..a37b490 100644
--- a/rtl/mips_cpu_control.v
+++ b/rtl/mips_cpu_control.v
@@ -96,7 +96,7 @@ always @(*) begin
     end else if ((op == JAL) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin
         CtrlRegDst = 2'd2; //const reg 31, for writing to the link register
         $display("CTRLREGDST: Link");
-    end else begin CtrlRegDst = 1'bx; $display("xxxxxxxxxxxxxx");end//Not all instructions are encompassed so, added incase for debug purposes
+    end else begin CtrlRegDst = 1'bx; end//Not all instructions are encompassed so, added incase for debug purposes
 
     //CtrlPC logic
     if(ALUCond && ((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL)))))begin
@@ -106,7 +106,7 @@ always @(*) begin
         $display("Jump PC Ctrl");
     end else if((op==SPECIAL)&&((funct==JR) || (funct==JALR)))begin
         CtrlPC = 2'd3; // Jumps using Register.
-        $display("Ctrl PC Jump Register");
+        //$display("Ctrl PC Jump Register");
     end else begin CtrlPC = 2'd0; /*/$display("Ctrl PC No Jump/Branch");*/end // No jumps or branches, just increment to next word
 
     //CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic where both are concerned. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled.
@@ -125,7 +125,7 @@ always @(*) begin
     end else if ((op==SPECIAL)&&(funct == MFLO))begin
         CtrlMemtoReg = 3'd4;//write data port of regfile is fed from ALULo
     end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
-    $display("OP: %d, Funct: %d", op, funct);
+    //$display("OP: %d, Funct: %d", op, funct);
     //CtrlALUOp Logic
     if((op==ADDIU) || ((op==SPECIAL)&&(funct==ADDU)))begin
         CtrlALUOp = 5'd0; //ADD from ALUOps
diff --git a/test/test_mips_cpu_custom.sh b/test/test_mips_cpu_custom.sh
deleted file mode 100755
index 0027de0..0000000
--- a/test/test_mips_cpu_custom.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/bash
-
-# arithmetic
-./test/test_mips_cpu_harvard.sh rtl addu             #Pass
-./test/test_mips_cpu_harvard.sh rtl addiu            #Pass
-./test/test_mips_cpu_harvard.sh rtl subu             #Pass
-./test/test_mips_cpu_harvard.sh rtl and              #Pass
-./test/test_mips_cpu_harvard.sh rtl andi             #Pass
-./test/test_mips_cpu_harvard.sh rtl or               #Pass
-./test/test_mips_cpu_harvard.sh rtl ori              #Pass
-./test/test_mips_cpu_harvard.sh rtl xor              #Pass
-./test/test_mips_cpu_harvard.sh rtl xori             #Pass
-./test/test_mips_cpu_harvard.sh rtl div              #Pass
-./test/test_mips_cpu_harvard.sh rtl divu             #pass
-./test/test_mips_cpu_harvard.sh rtl mthi             #Pass
-./test/test_mips_cpu_harvard.sh rtl mtlo             #Pass
-./test/test_mips_cpu_harvard.sh rtl mult             #Pass
-./test/test_mips_cpu_harvard.sh rtl multu            #Pass
-
-
-# branches
-./test/test_mips_cpu_harvard.sh rtl beq              #Pass
-./test/test_mips_cpu_harvard.sh rtl bgez             #Pass
-./test/test_mips_cpu_harvard.sh rtl bgezal           #Pass
-./test/test_mips_cpu_harvard.sh rtl bgtz             #Pass
-./test/test_mips_cpu_harvard.sh rtl blez             #Pass
-./test/test_mips_cpu_harvard.sh rtl bltz             #Pass
-./test/test_mips_cpu_harvard.sh rtl bltzal           #Pass
-./test/test_mips_cpu_harvard.sh rtl bne              #Pass
-
-# jumps
-./test/test_mips_cpu_harvard.sh rtl j                #Pass
-./test/test_mips_cpu_harvard.sh rtl jalr             #Pass
-./test/test_mips_cpu_harvard.sh rtl jal              #Pass
-./test/test_mips_cpu_harvard.sh rtl jr               #Pass
-
-# shift
-./test/test_mips_cpu_harvard.sh rtl sll              #Pass
-./test/test_mips_cpu_harvard.sh rtl srl              #Pass
-./test/test_mips_cpu_harvard.sh rtl sra              #Pass
-./test/test_mips_cpu_harvard.sh rtl srav             #Pass
-./test/test_mips_cpu_harvard.sh rtl sllv             #Pass
-./test/test_mips_cpu_harvard.sh rtl srlv             #Pass
-
-
-
-# load & store
-./test/test_mips_cpu_harvard.sh rtl lw               #Pass
-./test/test_mips_cpu_harvard.sh rtl lb               #Pass
-./test/test_mips_cpu_harvard.sh rtl lbu              #Pass
-./test/test_mips_cpu_harvard.sh rtl lh               #Pass
-./test/test_mips_cpu_harvard.sh rtl lhu              #Pass
-./test/test_mips_cpu_harvard.sh rtl lui              #Pass
-./test/test_mips_cpu_harvard.sh rtl lwl              #Pass
-./test/test_mips_cpu_harvard.sh rtl lwr              #Pass
-./test/test_mips_cpu_harvard.sh rtl sw               #Pass
-#./test/test_mips_cpu_harvard.sh rtl sb              #Once switched to bus
-#./test/test_mips_cpu_harvard.sh rtl sh              #Once switched to bus
-
-
-# set on less than **Branch delay slots dont work on these...
-./test/test_mips_cpu_harvard.sh rtl slti             #Pass
-./test/test_mips_cpu_harvard.sh rtl sltiu            #Pass
-./test/test_mips_cpu_harvard.sh rtl slt              #Pass
-./test/test_mips_cpu_harvard.sh rtl sltu             #Pass
-
-
diff --git a/testbench/mips_cpu_harvard_tb.v b/testbench/mips_cpu_harvard_tb.v
index 624f9c5..016d844 100644
--- a/testbench/mips_cpu_harvard_tb.v
+++ b/testbench/mips_cpu_harvard_tb.v
@@ -63,8 +63,8 @@ module mips_cpu_harvard_tb;
             @(posedge clk);
             //$display("Register v0: %d", register_v0);
             //$display("Reg File Write data: %d", cpuInst.in_writedata);
-            $display("Reg File Out Read data: %h", cpuInst.out_readdata1);
-            $display("Reg File opcode: %b", cpuInst.regfile.opcode);
+            //$display("Reg File Out Read data: %h", cpuInst.out_readdata1);
+            //$display("Reg File opcode: %b", cpuInst.regfile.opcode);
             //$display("ALU output: %h", cpuInst.out_ALURes);
             //$display("ALU input B: %h", cpuInst.alu.B);
         end

From cfebb403ba4de8ea15b8f9a3d8f4f0ace99411c8 Mon Sep 17 00:00:00 2001
From: jl7719 <jl7719@imperial.ac.uk>
Date: Thu, 17 Dec 2020 15:02:59 +0000
Subject: [PATCH 9/9] Delete  from source files and the testbench

---
 rtl/mips_cpu_alu.v              |  3 ---
 rtl/mips_cpu_control.v          | 26 +++-----------------------
 rtl/mips_cpu_harvard.v          |  1 -
 rtl/mips_cpu_regfile.v          |  4 ----
 test/test_mips_cpu_harvard.sh   |  2 +-
 testbench/mips_cpu_harvard_tb.v |  7 -------
 testbench/mips_cpu_memory.v     |  9 +--------
 7 files changed, 5 insertions(+), 47 deletions(-)

diff --git a/rtl/mips_cpu_alu.v b/rtl/mips_cpu_alu.v
index bc7fefe..132b5e6 100644
--- a/rtl/mips_cpu_alu.v
+++ b/rtl/mips_cpu_alu.v
@@ -135,7 +135,6 @@ end
 
       SLL: begin
           ALURes = B << shamt;
-          $display("ALURES SLL: %h", ALURes);
       end
 
       SLLV: begin
@@ -169,7 +168,6 @@ end
       end
 
       LES: begin
-          $display("ALU A: %h B: %h", $signed(A), $signed(B));
           if ($signed(A) < $signed(B)) begin
             ALUCond = 1;
           end
@@ -248,7 +246,6 @@ end
       end
 
       DIVU: begin
-        $display("ALU A: %h B: %h", A, B);
           temp_Lo = A / B;
           temp_Hi = A % B;
       end
diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v
index a37b490..83f28c7 100644
--- a/rtl/mips_cpu_control.v
+++ b/rtl/mips_cpu_control.v
@@ -89,13 +89,10 @@ always @(*) begin
     //CtrlRegDst logic
     if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI))begin
         CtrlRegDst = 2'd0; //Write address comes from rt
-        $display("CTRLREGDST: Rt");
     end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin
         CtrlRegDst = 2'd1; //Write address comes from rd
-        $display("CTRLREGDST: Rd");
     end else if ((op == JAL) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin
         CtrlRegDst = 2'd2; //const reg 31, for writing to the link register
-        $display("CTRLREGDST: Link");
     end else begin CtrlRegDst = 1'bx; end//Not all instructions are encompassed so, added incase for debug purposes
 
     //CtrlPC logic
@@ -103,21 +100,17 @@ always @(*) begin
         CtrlPC = 2'd1; // Branches - Jumps relative to PC
     end else if((op==J) || (op==JAL))begin
         CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
-        $display("Jump PC Ctrl");
     end else if((op==SPECIAL)&&((funct==JR) || (funct==JALR)))begin
         CtrlPC = 2'd3; // Jumps using Register.
-        //$display("Ctrl PC Jump Register");
-    end else begin CtrlPC = 2'd0; /*/$display("Ctrl PC No Jump/Branch");*/end // No jumps or branches, just increment to next word
-
+    end else begin CtrlPC = 2'd0; end // No jumps or branches, just increment to next word
+    
     //CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic where both are concerned. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled.
     if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR))begin
         CtrlMemRead = 1;//Memory is read enabled
         CtrlMemtoReg = 3'd1;//write data port of regfile is fed from data memory
-        $display("Memory read enabled");
     end else if ((op==ADDIU) || (op==ANDI) || (op==ORI) || (op==LUI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) ||  (funct==OR) ||  (funct==SLL) ||  (funct==SLLV) ||  (funct==SLT) ||  (funct==SLTU) ||  (funct==SRA) ||  (funct==SRAV) ||  (funct==SRL) || (funct==SRLV) ||  (funct==SUBU) ||  (funct==XOR))))begin
         CtrlMemRead = 0;//Memory is read disabled
         CtrlMemtoReg = 3'd0;//write data port of regfile is fed from ALURes
-        $display("Memory read disabled");
     end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin
         CtrlMemtoReg = 3'd2;//write data port of regfile is fed from PC + 8
     end else if ((op==SPECIAL)&&(funct == MFHI))begin
@@ -125,11 +118,10 @@ always @(*) begin
     end else if ((op==SPECIAL)&&(funct == MFLO))begin
         CtrlMemtoReg = 3'd4;//write data port of regfile is fed from ALULo
     end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
-    //$display("OP: %d, Funct: %d", op, funct);
+
     //CtrlALUOp Logic
     if((op==ADDIU) || ((op==SPECIAL)&&(funct==ADDU)))begin
         CtrlALUOp = 5'd0; //ADD from ALUOps
-        $display("ALU OP = 0 (ADDU/ADDIU)");
     end else if((op==ANDI) || ((op==SPECIAL)&&(funct==AND)))begin
         CtrlALUOp = 5'd4;//AND from ALUOps
     end else if(op==BEQ) begin
@@ -146,12 +138,10 @@ always @(*) begin
         CtrlALUOp = 5'd18;//NEQ from ALUOps
     end else if((op==SPECIAL)&&(funct==DIV))begin
         CtrlALUOp = 5'd3;//DIV from ALUOps
-        $display("DIV CONTROL ALUOps");
     end else if((op==SPECIAL)&&(funct==DIVU))begin
         CtrlALUOp = 5'd23;//DIVU from ALUOps
     end else if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin
         CtrlALUOp = 5'd0;//ADD from ALUOps
-        $display("LB IN CONTROL");
     end else if(op==LUI)begin
         CtrlALUOp = 5'd7;//SLL from ALUOps
     end else if((op==SPECIAL)&&((funct==MTHI)))begin
@@ -166,31 +156,24 @@ always @(*) begin
         CtrlALUOp = 5'd5;//OR from ALUOps
     end else if((op==SPECIAL)&&(funct==SLL))begin
         CtrlALUOp = 5'd7;//SLL from ALUOps
-        $display("ALU Op = 7 (SLL)");
     end else if((op==SPECIAL)&&(funct==SLLV))begin
         CtrlALUOp = 5'd8;//SLLV from ALUOps
-        $display("ALU Op = 9 (SLLV)");
     end else if((op==SPECIAL)&&(funct==SRA))begin
         CtrlALUOp = 5'd11;//SRA from ALUOps
-        $display("ALU Op = 11 (SRA)");
     end else if((op==SPECIAL)&&(funct==SRAV))begin
         CtrlALUOp = 5'd12;//SRAV from ALUOps
     end else if((op==SPECIAL)&&(funct==SRL))begin
-        $display("ALU Op = 7 (SRL)");
         CtrlALUOp = 5'd9;//SRL from ALUOps
     end else if((op==SPECIAL)&&(funct==SRLV))begin
         CtrlALUOp = 5'd10;//SRLV from ALUOps
     end else if((op==SLTI) || ((op==SPECIAL)&&(funct==SLT)))begin
         CtrlALUOp = 5'd20;//SLT from ALUOps
-        $display("ALU Op = 20 (SLT/SLTI)");
     end else if((op==SLTIU) || ((op==SPECIAL)&&(funct==SLTU)))begin
         CtrlALUOp = 5'd21;//SLTU from ALUOps
-        $display("ALU Op = 21 (SLTU/SLTIU)");
     end else if((op==SPECIAL)&&(funct==SUBU))begin
         CtrlALUOp = 5'd1;//SUB from ALUOps
     end else if((op==XORI) || ((op==SPECIAL)&&(funct==XOR)))begin
         CtrlALUOp = 5'd6;//XOR from ALUOps
-        $display("ALU Op = 6 (XOR)");
     end else begin
         CtrlALUOp = 5'bxxxxx;
     end
@@ -200,7 +183,6 @@ always @(*) begin
         Ctrlshamt = Instr[10:6];// Shift amount piped in from the instruction
     end else if(op == LUI)begin
         Ctrlshamt = 5'd16;//Used specifically to implement LUI as the instruction itslef does not include shamt
-        $display("LUI SHIFTING");
     end else begin Ctrlshamt = 5'bxxxxx;end
 
     //CtrlMemWrite logic
@@ -211,7 +193,6 @@ always @(*) begin
     //CtrlSpcRegWriteEn logic
     if((op==SPECIAL)&&((funct==MTHI) || (funct==MTLO) || (funct==MULT) || (funct==MULTU) || (funct==DIV) || (funct==DIVU)))begin
         CtrlSpcRegWriteEn = 1;//Special register Hi and Lo are write enabled
-        $display("Temp being written");
     end else begin CtrlSpcRegWriteEn = 0;end//default is 0 to ensure no accidental overwriting.
     
     //CtrlALUSrc logic
@@ -226,7 +207,6 @@ always @(*) begin
     //CtrlRegWrite logic
     if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
         CtrlRegWrite = 1;//The Registers are Write Enabled
-        $display("OPcode mflo: %h", op);
     end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
 end
 endmodule
\ No newline at end of file
diff --git a/rtl/mips_cpu_harvard.v b/rtl/mips_cpu_harvard.v
index ae21b3c..80d6a4a 100644
--- a/rtl/mips_cpu_harvard.v
+++ b/rtl/mips_cpu_harvard.v
@@ -61,7 +61,6 @@ always @(*) begin
         end
         3'd2:begin
             in_writedata = (out_pc_out + 32'd8);//Output from PC +8.
-            $display("LINKING-----------<: %h", in_writedata);
         end
         3'd3:begin
             in_writedata = (out_ALUHi);
diff --git a/rtl/mips_cpu_regfile.v b/rtl/mips_cpu_regfile.v
index c27fa69..6d27df6 100644
--- a/rtl/mips_cpu_regfile.v
+++ b/rtl/mips_cpu_regfile.v
@@ -29,7 +29,6 @@ always_ff @(negedge clk) begin
 	if (writereg == 5'b00000) begin
 		// skip writing if rd is $0
 	end else if (regwrite) begin
-		$display("%b", opcode);
 		case (opcode)
 			6'b100000: begin //lb, load byte
 				case (readdata1[1:0])	
@@ -38,8 +37,6 @@ always_ff @(negedge clk) begin
 					2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]};
 					2'b11: memory[writereg] <= {{24{writedata[31]}}, writedata[31:24]};
 				endcase // readdata1[1:0]
-				$display("writedata %h", writedata);
-				$display("memory writereg %h", memory[writereg]);
 			end
 			6'b100100: begin //lbu, load byte unsigned
 				case (readdata1[1:0])
@@ -79,7 +76,6 @@ always_ff @(negedge clk) begin
 			end
 			default: begin 
 				memory[writereg] <= writedata; //most instructions
-				$display("Write %d in regfile", writedata);
 			end
 		endcase // opcode
 	end
diff --git a/test/test_mips_cpu_harvard.sh b/test/test_mips_cpu_harvard.sh
index e5cd348..3adf52f 100755
--- a/test/test_mips_cpu_harvard.sh
+++ b/test/test_mips_cpu_harvard.sh
@@ -47,7 +47,7 @@ else
         -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \
         -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \
         -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_memory.v\
-        ${SRC} 2> /dev/null
+        ${SRC} #2> /dev/null
         ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt;             # log file for debugging (contains $display)
         echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt;      # register v0 output to compare with reference
         if diff -w ./inputs/${INSTR}/${TESTCASE}.out.txt ./inputs/${INSTR}/${TESTCASE}.ref.txt &> /dev/null   # compare
diff --git a/testbench/mips_cpu_harvard_tb.v b/testbench/mips_cpu_harvard_tb.v
index 016d844..85ca66e 100644
--- a/testbench/mips_cpu_harvard_tb.v
+++ b/testbench/mips_cpu_harvard_tb.v
@@ -59,14 +59,7 @@ module mips_cpu_harvard_tb;
         else $display("TB: CPU did not set active=1 after reset.");
 
         while (active) begin
-            //$display("Clk: %d", clk);
             @(posedge clk);
-            //$display("Register v0: %d", register_v0);
-            //$display("Reg File Write data: %d", cpuInst.in_writedata);
-            //$display("Reg File Out Read data: %h", cpuInst.out_readdata1);
-            //$display("Reg File opcode: %b", cpuInst.regfile.opcode);
-            //$display("ALU output: %h", cpuInst.out_ALURes);
-            //$display("ALU input B: %h", cpuInst.alu.B);
         end
         @(posedge clk);
         $display("TB: CPU Halt; active=0");
diff --git a/testbench/mips_cpu_memory.v b/testbench/mips_cpu_memory.v
index 230b311..bfd8e56 100644
--- a/testbench/mips_cpu_memory.v
+++ b/testbench/mips_cpu_memory.v
@@ -56,16 +56,9 @@ module mips_cpu_memory(
 
     //Synchronous write path
     always_ff @(posedge clk) begin
-        //$display("Instruction: %h", instr_readdata);
-        //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
         if (data_write) begin              //cannot read and write to memory in the same cycle
             if (instr_address != data_address) begin    //cannot modify the instruction being read
-                data_memory[(data_address-32'h00001000)>>2] <= data_writedata; 
-                $display("Store in memory");     
-                $display(data_writedata);      
-            end
-            for (integer k = 0; k<$size(data_memory); k++) begin
-            $display("byte +%h: %h", 32'h00001000+k*4, data_memory[k]);
+                data_memory[(data_address-32'h00001000)>>2] <= data_writedata;    
             end
         end