mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-11-12 18:55:48 +00:00
Update to test each instruction with a small memory
This commit is contained in:
jl7719
parent
6becea322f
commit
c5aed43ab4
8
inputs/ori.txt
Normal file
8
inputs/ori.txt
Normal file
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@ -0,0 +1,8 @@
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34040003
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00000008
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00000000
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00000000
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00000000
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00000000
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00000000
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00000000
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@ -1,5 +1,4 @@
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module mips_cpu_control(
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input logic[31:0] Instr,
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input logic ALUCond,
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@ -12,17 +11,8 @@ module mips_cpu_control(
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output logic CtrlMemWrite,
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output logic CtrlALUSrc,
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output logic CtrlRegWrite
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);
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/* logic[5:0] op;
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logic[5:0] funct;
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logic[4:0] rt; */
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/* assign op = Instr[31:26];
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assign funct = Instr[5:0];
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assign rt = Instr[20:16]; */
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typedef enum logic[5:0]{
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SPECIAL = 6'd0,
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REGIMM = 6'd1,
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@ -89,115 +79,119 @@ typedef enum logic[4:0]{
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rt_enum rt;
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assign rt = Instr[20:16];
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always_comb begin
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always @(*) begin
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//CtrlRegDst logic
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if(op == (ADDIU | ANDI | LB | LBU | LH | LHU | LUI | LW | LWL | LWR | ORI | SLTI | SLTIU | XORI))begin
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if((op == ADDIU | op == ANDI | op == LB | op == LBU | op == LH | op == LHU | op == LUI | op == LW | op == LWL | op == LWR | op == ORI | op == SLTI | op == SLTIU | op == XORI))begin
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CtrlRegDst = 2'd0; //Write address comes from rt
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end else if (op == (SPECIAL & (funct == (ADDU | AND | JALR | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR))))begin
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end else if ((op == SPECIAL) & ((funct == ADDU | funct == AND | funct == JALR | funct == OR | funct == SLL | funct == SLLV | funct == SLT | funct == SLTU | funct == SRA | funct == SRAV | funct == SRL | funct == SRLV | funct == SUBU | funct == XOR)))begin
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CtrlRegDst = 2'd1; //Write address comes from rd
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end else if (op == JAL)begin
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CtrlRegDst = 2'd2; //const reg 31, for writing to the link register
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end else begin CtrlRegDst = 1'bx; end//Not all instructions are encompassed so, added incase for debug purposes
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//CtrlPC logic
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if(ALUCond & (op == (BEQ | BGTZ | BLEZ | BNE | (REGIMM & (rt == (BGEZ | BGEZAL | BLTZ | BLTZAL))))))begin
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if(ALUCond & ( (op == BEQ | op == BGTZ | op ==BLEZ | op ==BNE | (op == REGIMM & ((rt == BGEZ | rt == BGEZAL | rt == BLTZ | rt == BLTZAL))))))begin
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CtrlPC = 2'd1; // Branches - Jumps relative to PC
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end else if(op == (J | JAL))begin
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$display("Ctrl PC Branch");
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end else if( (op == J | op == JAL))begin
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CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
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end else if(op == (JR | JALR))begin
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$display("Ctrl PC Jump Immediate");
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end else if((funct == JR | funct == JALR))begin
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CtrlPC = 2'd3; // Jumps using Register.
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end else begin CtrlPC = 2'd0;end // No jumps or branches, just increment to next word
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$display("Ctrl PC Jump Register");
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end else begin CtrlPC = 2'd0; $display("Ctrl PC No Jump/Branch");end // No jumps or branches, just increment to next word
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//CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled.
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if(op == (LB | LBU | LH | LHU | LW | LWL | LWR))begin
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if((op == LB | op == LBU | op == LH | op == LHU | op == LW | op == LWL | op == LWR))begin
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CtrlMemRead = 1;//Memory is read enabled
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CtrlMemtoReg = 2'd1;//write data port of memory is fed from data memory
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end else if (op == (ADDIU | ANDI | ORI | SLTI | SLTIU | XORI | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MTHI | MTLO | MULT | MULTU | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR)))))begin
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end else if ((op == ADDIU | op == ANDI | op == ORI | op == SLTI | op == SLTIU | op == XORI | (op == SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MTHI | MTLO | MULT | MULTU | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR)))))begin
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CtrlMemRead = 0;//Memory is read disabled
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CtrlMemtoReg = 2'd0;//write data port of memory is fed from ALURes
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end else if (op == (JAL | (SPECIAL &(funct == JALR))))begin
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end else if ((op == JAL) | ((op == SPECIAL) & (funct == JALR)))begin
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CtrlMemtoReg = 2'd2;//write data port of memory is fed from PC + 8
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end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
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//CtrlALUOp Logic
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if(op == (ADDIU | (SPECIAL & (funct == ADDU))))begin
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if((op == ADDIU | (op == SPECIAL & (funct == ADDU))))begin
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CtrlALUOp = 5'd0; //ADD from ALUOps
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end else if (op == (ANDI | (SPECIAL & (funct == AND))))begin
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end else if ((op == ANDI | (op == SPECIAL & (funct == AND))))begin
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CtrlALUOp = 5'd4;//AND from ALUOps
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end else if (op == BEQ) begin
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CtrlALUOp = 5'd13;//EQ from ALUOps
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end else if (op == (REGIMM & (rt == (BGEZ | BGEZAL))))begin
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end else if ((op == REGIMM & ((rt == BGEZ | rt == BGEZAL))))begin
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CtrlALUOp = 5'd17;//GEQ from ALUOps
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end else if (op == BGTZ)begin
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CtrlALUOp = 5'd16;//GRT from ALUOps
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end else if (op == BLEZ)begin
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CtrlALUOp = 5'd15;//LEQ from ALUOps
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end else if (op == (REGIMM & (rt == (BLTZ | BLTZAL))))begin
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end else if ((op == REGIMM & ((rt == BLTZ | rt == BLTZAL))))begin
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CtrlALUOp = 5'd14;//LES from ALUOps
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end else if (OP == BNE)begin
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end else if (op == BNE)begin
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CtrlALUOp = 5'd18;//NEQ from ALUOps
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end else if (op == (SPECIAL & (funct == DIV)))begin
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end else if ((op == SPECIAL & (funct == DIV)))begin
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CtrlALUOp = 5'd3;//DIV from ALUOps
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end else if (op == (SPECIAL & (funct == DIVU)))begin
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end else if ((op == SPECIAL & (funct == DIVU)))begin
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CtrlALUOp = 5'd23;//DIVU from ALUOps
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end else if (op == (LB | LBU | LH | LHU | LW | LWL | LWR | SB | SBH | SW))begin
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end else if ((op == LB | op == LBU | op == LH | op == LHU | op == LW | op == LWL | op == LWR | op == SB | op == SH | op == SW))begin
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CtrlALUOp = 5'd0;//ADD from ALUOps
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end else if (op == LUI)begin
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CtrlALUOp = 5'd7;//SLL from ALUOps
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end else if (op == (SPECIAL & (funct == MTHI | MTLO)))begin
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end else if ((op == SPECIAL & (funct == MTHI | MTLO)))begin
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CtrlALUOp = 5'd19;//PAS from ALUOps
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end else if (op == (SPECIAL & (funct == MULT)))begin
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end else if ((op == SPECIAL & (funct == MULT)))begin
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CtrlALUOp = 5'd2;//MUL from ALUOps
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end else if (op == (SPECIAL & (funct == MULTU)))begin
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end else if ((op == SPECIAL & (funct == MULTU)))begin
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CtrlALUOp = 5'd22;//MULU from ALUOps
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end else if (op == (ORI | (SPECIAL & (funct == OR))))begin
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end else if ((op == ORI | (op == SPECIAL & (funct == OR))))begin
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CtrlALUOp = 5'd5;//OR from ALUOps
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end else if (op == (SPECIAL & (funct == SLL)))begin
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end else if (op == SPECIAL & (funct == SLL))begin
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CtrlALUOp = 5'd7;//SLL from ALUOps
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end else if (op == (SPECIAL & (funct == SLLV)))begin
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end else if (op == SPECIAL & (funct == SLLV))begin
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CtrlALUOp = 5'd8;//SLLV from ALUOps
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end else if (op == (SPECIAL & (funct == SRA)))begin
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end else if (op == SPECIAL & (funct == SRA))begin
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CtrlALUOp = 5'd11;//SRA from ALUOps
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end else if (op == (SPECIAL & (funct == SRAV)))begin
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end else if (op == SPECIAL & (funct == SRAV))begin
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CtrlALUOp = 5'd12;//SRAV from ALUOps
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end else if (op == (SPECIAL & (funct == SRL)))begin
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end else if (op == SPECIAL & (funct == SRL))begin
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CtrlALUOp = 5'd9;//SRL from ALUOps
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end else if (op == (SPECIAL & (funct == SRLV)))begin
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end else if (op == SPECIAL & (funct == SRLV))begin
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CtrlALUOp = 5'd10;//SRLV from ALUOps
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end else if (op == (SLTI | (SPECIAL & (funct == SLT))))begin
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end else if (op == SLTI | (op == SPECIAL & (funct == SLT)))begin
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CtrlALUOp = 5'd20;//SLT from ALUOps
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end else if (op == (SLTIU | (SPECIAL & (funct == SLTU))))begin
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end else if (op == SLTIU | (op == SPECIAL & (funct == SLTU)))begin
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CtrlALUOp = 5'd21;//SLTU from ALUOps
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end else if (op == (SPECIAL & (funct == SUBU)))begin
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end else if (op == SPECIAL & (funct == SUBU))begin
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CtrlALUOp = 5'd1;//SUB from ALUOps
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end else if (op == (XORI | (SPECIAL & (funct == XOR))))begin
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end else if (op == XORI | (op == SPECIAL & (funct == XOR)))begin
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CtrlALUOp = 5'd6;//XOR from ALUOps
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end else begin
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CtrlALUOp = 5'bxxxxx;
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end
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//Ctrlshamt logic
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if(op == (SPECIAL & (funct == (SRA | SRL | SLL))))begin
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if(op == SPECIAL & (funct == (SRA | SRL | SLL)))begin
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Ctrlshamt = Instr[10:6];// Shift amount piped in from the instruction
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end else if(op == LUI)begin
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Ctrlshamt = 5'd16;//Used specifically to implement LUI as the instruction itslef does not include shamt
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end else begin Ctrlshamt = 5'bxxxxx;end
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//CtrlMemWrite logic
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if(op == (SB | SH | SW))begin
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if(op == SB | op == SH | op == SW)begin
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CtrlMemWrite = 1;//Memory is write enabled
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end else begin CtrlMemWrite = 0;end//default is 0 to ensure no accidental overwriting.
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//CtrlALUSrc logic
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if(op == (ADDIU | ANDI | LUI | ORI | SLTI | SLTIU | XORI | LB | LBU | LH | LHU | LW | LWL | LWR | SB | SH | SW))begin
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if((op == ADDIU | op == ANDI | op == LUI | op == ORI | op == SLTI | op == SLTIU | op == XORI | op == LB | op == LBU | op == LH | op == LHU | op == LW | op == LWL | op == LWR | op == SB | op == SH | op == SW))begin
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CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0]
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end else if (op == (BEQ | BGTZ | BLEZ | BNE | (REGIMM & (rt == (BGEZ | BGEZAL | BLTZ | BLTZAL))) | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MULT | MULTU | OR | SLLV | SLT | SLTU | SRAV | SRLV | SUBU | XOR)))))begin
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end else if ((op == BEQ | op == BGTZ | op == BLEZ | op == BNE | (op == REGIMM & ((rt == BGEZ | rt == BGEZAL | rt == BLTZ | rt == BLTZAL))) | (op == SPECIAL & ((funct == ADDU | funct == AND | funct == DIV | funct == DIVU | funct == MULT | funct == MULTU | funct == OR | funct == SLLV | funct == SLT | funct == SLTU | funct == SRAV | funct == SRLV | funct == SUBU | funct == XOR)))))begin
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CtrlALUSrc = 0;///ALU Bus B is fed from rt.
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end else begin CtrlALUSrc = 1'bx;end
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//CtrlRegWrite logic
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if(op == (ADDIU | ANDI | LB | LBU | LH | LHU | LUI | LW | LWL | LWR | ORI | SLTI | SLTIU | XORI | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MULT | MULTU | JALR | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR)))))begin
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if((op == ADDIU | op == ANDI | op == LB | op == LBU | op == LH | op == LHU | op == LUI | op == LW | op == LWL | op == LWR | op == ORI | op == SLTI | op == SLTIU | op == XORI | (op == SPECIAL & ((funct == ADDU | funct == AND | funct == DIV | funct == DIVU | funct == MULT | funct == MULTU | funct == JALR | funct == OR | funct == SLL | funct == SLLV | funct == SLT | funct == SLTU | funct == SRA | funct == SRAV | funct == SRL | funct == SRLV | funct == SUBU | funct == XOR)))))begin
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CtrlRegWrite = 1;//The Registers are Write Enabled
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end else begin CtrlRegWrite = 0; end // The Registers are Write Disabled
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@ -31,36 +31,34 @@ module mips_cpu_memory(
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);
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parameter RAM_INIT_FILE = "";
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reg [31:0] memory [4294967295:0]; // 2^32 memory locations of 32 bits size
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reg [31:0] memory [0:7]; // 2^30 set as 8 for now for small testcases
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initial begin
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integer i;
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//Initialise to zero by default
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for (i=0; i<4294967296; i++) begin
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for (i=0; i<8; i++) begin
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memory[i]=0;
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end
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//Load contents from file if specified
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if (RAM_INIT_FILE != "") begin
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$display("RAM : INIT : Loading RAM contents from %s", RAM_INIT_FILE);
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$readmemh(RAM_INIT_FILE, memory, 32'hBFC00000, 32'd0);
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$display("RAM: Loading RAM contents from %s", RAM_INIT_FILE);
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$readmemh(RAM_INIT_FILE, memory, 32'h4); //32'hBFC00000 equivalent for small memory as byte 16
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end
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//Display what's in memory for debugging
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for (integer j = 0; j<$size(memory); j++) begin
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$display("Byte %d, %h", j*4, memory[j]);
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end
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end
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//Combinatorial read path for data and instruction.
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always_comb begin
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if (clk == 1'd1) begin
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data_readdata = data_read ? memory[data_address] : 16'hxxxx;
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instr_readdata = memory[instr_address];
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end
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else begin
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data_readdata = data_readdata;
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instr_readdata = instr_address;
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end
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end
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assign data_readdata = data_read ? {memory[data_address],memory[data_address+1],memory[data_address+2],memory[data_address+3]} : 16'hxxxx;
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assign instr_readdata = memory[instr_address/4];
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//Synchronous write path
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always_ff @(posedge clk) begin
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$display("Instruction Read: %h", instr_readdata);
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//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
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if (!data_read & data_write) begin //cannot read and write to memory in the same cycle
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if (instr_address != data_address) begin //cannot modify the instruction being read
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@ -70,3 +68,4 @@ module mips_cpu_memory(
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end
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endmodule
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@ -23,41 +23,30 @@ echo ${INSTR};
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if [[ ${INSTR} == "No instruction specified: running all testcases" ]];
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then
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# All Testcase Files
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TESTCASES=$(ls ./inputs | grep ".hex.txt");
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TESTCASES=$(ls ./inputs | grep ".txt");
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echo ${TESTCASES}
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for TESTCASE in ${TESTCASES}
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do
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# Run Each Testcase File
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echo ${TESTCASE}
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#iverilog -g 2012 \
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# -s mips_cpu_harvard_tb \
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# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/"${TESTCASE}\" \
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# -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
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# ${SRC}
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/mnt/c/Windows/System32/cmd.exe /C \
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iverilog -Wall -g2012 \
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-s mips_cpu_harvard_tb \
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-P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${TESTCASE}.txt\" \
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-o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \
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${SRC}
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/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${TESTCASE};
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done
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else
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echo ${INSTR};
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# Run Testcase File Of Specified Instruction
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# Windows Iverilog with WSL
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#/mnt/c/Windows/System32/cmd.exe /C iverilog -g2012 \
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# -s mips_cpu_harvard_tb \
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# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
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# -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
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# ${SRC}
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# Linux Iverilog
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iverilog -g2012 \
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echo ${INSTR};
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/mnt/c/Windows/System32/cmd.exe /C \
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iverilog -Wall -g2012 \
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-s mips_cpu_harvard_tb \
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-P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
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-o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
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-o exec/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
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${SRC}
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/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${INSTR};
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fi
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#/mnt/c/Windows/System32/cmd.exe /C \ # need this to run verilog on windows
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#iverilog -g 2012 \
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# -s mips_cpu_harvard_tb \
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# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/addiu.hex.txt\" \
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# -o program/mips_cpu_harvard_tb testbench/mips_cpu_harvard_tb.v test/mips_cpu_harvard.v \
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# test/mips_cpu_control.v test/mips_cpu_alu.v test/mips_cpu_memory.v test/mips_cpu_regfile.v test/mips_cpu_pc.v
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@ -1,14 +1,10 @@
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module mips_cpu_harvard_tb;
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timeunit 1ns / 10ps;
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parameter RAM_INIT_FILE = "inputs/";
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parameter TIMEOUT_CYCLES = 10000;
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parameter RAM_INIT_FILE = "inputs/addu.txt";
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parameter TIMEOUT_CYCLES = 100;
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logic clk, clk_enable, reset, active;
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logic[31:0] register_v0;
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logic[31:0] instr_address, instr_readdata;
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logic data_read, data_write;
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logic[31:0] data_readdata, data_writedata, data_address;
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logic clk, clk_enable, reset, active, data_read, data_write;
|
||||
logic[31:0] register_v0, instr_address, instr_readdata, data_readdata, data_writedata, data_address;
|
||||
|
||||
mips_cpu_memory #(RAM_INIT_FILE) ramInst(
|
||||
.clk(clk),
|
||||
|
|
@ -50,24 +46,29 @@ module mips_cpu_harvard_tb;
|
|||
end
|
||||
|
||||
initial begin
|
||||
$display("Initial Reset 0");
|
||||
reset <= 0;
|
||||
|
||||
|
||||
$display("Initial Reset 1");
|
||||
@(posedge clk);
|
||||
reset <= 1;
|
||||
|
||||
$display("Initial Reset 0: Start Program");
|
||||
@(posedge clk);
|
||||
reset <= 0;
|
||||
|
||||
@(posedge clk);
|
||||
assert(active==1) // Is this assert still valid?
|
||||
assert(active==1);
|
||||
else $display("TB: CPU did not set active=1 after reset.");
|
||||
|
||||
while (active) begin
|
||||
@(posedge clk);
|
||||
$display("Register v0: %d", register_v0);
|
||||
end
|
||||
|
||||
$display("TB : finished; running=0");
|
||||
$display("%d",register_v0);
|
||||
$display("TB: finished; active=0");
|
||||
$display("Output: %d", register_v0);
|
||||
$finish;
|
||||
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in a new issue