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Update to test each instruction with a small memory

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jl7719 2020-12-09 16:47:58 +09:00
parent 6becea322f
commit c5aed43ab4
5 changed files with 96 additions and 105 deletions
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8
inputs/ori.txt Normal file
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@ -0,0 +1,8 @@
34040003
00000008
00000000
00000000
00000000
00000000
00000000
00000000

88
rtl/mips_cpu_control.v
View file

@ -1,5 +1,4 @@
module mips_cpu_control( module mips_cpu_control(
input logic[31:0] Instr, input logic[31:0] Instr,
input logic ALUCond, input logic ALUCond,
@ -12,17 +11,8 @@ module mips_cpu_control(
output logic CtrlMemWrite, output logic CtrlMemWrite,
output logic CtrlALUSrc, output logic CtrlALUSrc,
output logic CtrlRegWrite output logic CtrlRegWrite
); );
/* logic[5:0] op;
logic[5:0] funct;
logic[4:0] rt; */
/* assign op = Instr[31:26];
assign funct = Instr[5:0];
assign rt = Instr[20:16]; */
typedef enum logic[5:0]{ typedef enum logic[5:0]{
SPECIAL = 6'd0, SPECIAL = 6'd0,
REGIMM = 6'd1, REGIMM = 6'd1,
@ -89,115 +79,119 @@ typedef enum logic[4:0]{
rt_enum rt; rt_enum rt;
assign rt = Instr[20:16]; assign rt = Instr[20:16];
always_comb begin
always @(*) begin
//CtrlRegDst logic //CtrlRegDst logic
if(op == (ADDIU | ANDI | LB | LBU | LH | LHU | LUI | LW | LWL | LWR | ORI | SLTI | SLTIU | XORI))begin if((op == ADDIU | op == ANDI | op == LB | op == LBU | op == LH | op == LHU | op == LUI | op == LW | op == LWL | op == LWR | op == ORI | op == SLTI | op == SLTIU | op == XORI))begin
CtrlRegDst = 2'd0; //Write address comes from rt CtrlRegDst = 2'd0; //Write address comes from rt
end else if (op == (SPECIAL & (funct == (ADDU | AND | JALR | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR))))begin end else if ((op == SPECIAL) & ((funct == ADDU | funct == AND | funct == JALR | funct == OR | funct == SLL | funct == SLLV | funct == SLT | funct == SLTU | funct == SRA | funct == SRAV | funct == SRL | funct == SRLV | funct == SUBU | funct == XOR)))begin
CtrlRegDst = 2'd1; //Write address comes from rd CtrlRegDst = 2'd1; //Write address comes from rd
end else if (op == JAL)begin end else if (op == JAL)begin
CtrlRegDst = 2'd2; //const reg 31, for writing to the link register CtrlRegDst = 2'd2; //const reg 31, for writing to the link register
end else begin CtrlRegDst = 1'bx; end//Not all instructions are encompassed so, added incase for debug purposes end else begin CtrlRegDst = 1'bx; end//Not all instructions are encompassed so, added incase for debug purposes
//CtrlPC logic //CtrlPC logic
if(ALUCond & (op == (BEQ | BGTZ | BLEZ | BNE | (REGIMM & (rt == (BGEZ | BGEZAL | BLTZ | BLTZAL))))))begin if(ALUCond & ( (op == BEQ | op == BGTZ | op ==BLEZ | op ==BNE | (op == REGIMM & ((rt == BGEZ | rt == BGEZAL | rt == BLTZ | rt == BLTZAL))))))begin
CtrlPC = 2'd1; // Branches - Jumps relative to PC CtrlPC = 2'd1; // Branches - Jumps relative to PC
end else if(op == (J | JAL))begin $display("Ctrl PC Branch");
end else if( (op == J | op == JAL))begin
CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
end else if(op == (JR | JALR))begin $display("Ctrl PC Jump Immediate");
end else if((funct == JR | funct == JALR))begin
CtrlPC = 2'd3; // Jumps using Register. CtrlPC = 2'd3; // Jumps using Register.
end else begin CtrlPC = 2'd0;end // No jumps or branches, just increment to next word $display("Ctrl PC Jump Register");
end else begin CtrlPC = 2'd0; $display("Ctrl PC No Jump/Branch");end // No jumps or branches, just increment to next word
//CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled. //CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled.
if(op == (LB | LBU | LH | LHU | LW | LWL | LWR))begin if((op == LB | op == LBU | op == LH | op == LHU | op == LW | op == LWL | op == LWR))begin
CtrlMemRead = 1;//Memory is read enabled CtrlMemRead = 1;//Memory is read enabled
CtrlMemtoReg = 2'd1;//write data port of memory is fed from data memory CtrlMemtoReg = 2'd1;//write data port of memory is fed from data memory
end else if (op == (ADDIU | ANDI | ORI | SLTI | SLTIU | XORI | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MTHI | MTLO | MULT | MULTU | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR)))))begin end else if ((op == ADDIU | op == ANDI | op == ORI | op == SLTI | op == SLTIU | op == XORI | (op == SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MTHI | MTLO | MULT | MULTU | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR)))))begin
CtrlMemRead = 0;//Memory is read disabled CtrlMemRead = 0;//Memory is read disabled
CtrlMemtoReg = 2'd0;//write data port of memory is fed from ALURes CtrlMemtoReg = 2'd0;//write data port of memory is fed from ALURes
end else if (op == (JAL | (SPECIAL &(funct == JALR))))begin end else if ((op == JAL) | ((op == SPECIAL) & (funct == JALR)))begin
CtrlMemtoReg = 2'd2;//write data port of memory is fed from PC + 8 CtrlMemtoReg = 2'd2;//write data port of memory is fed from PC + 8
end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
//CtrlALUOp Logic //CtrlALUOp Logic
if(op == (ADDIU | (SPECIAL & (funct == ADDU))))begin if((op == ADDIU | (op == SPECIAL & (funct == ADDU))))begin
CtrlALUOp = 5'd0; //ADD from ALUOps CtrlALUOp = 5'd0; //ADD from ALUOps
end else if (op == (ANDI | (SPECIAL & (funct == AND))))begin end else if ((op == ANDI | (op == SPECIAL & (funct == AND))))begin
CtrlALUOp = 5'd4;//AND from ALUOps CtrlALUOp = 5'd4;//AND from ALUOps
end else if (op == BEQ) begin end else if (op == BEQ) begin
CtrlALUOp = 5'd13;//EQ from ALUOps CtrlALUOp = 5'd13;//EQ from ALUOps
end else if (op == (REGIMM & (rt == (BGEZ | BGEZAL))))begin end else if ((op == REGIMM & ((rt == BGEZ | rt == BGEZAL))))begin
CtrlALUOp = 5'd17;//GEQ from ALUOps CtrlALUOp = 5'd17;//GEQ from ALUOps
end else if (op == BGTZ)begin end else if (op == BGTZ)begin
CtrlALUOp = 5'd16;//GRT from ALUOps CtrlALUOp = 5'd16;//GRT from ALUOps
end else if (op == BLEZ)begin end else if (op == BLEZ)begin
CtrlALUOp = 5'd15;//LEQ from ALUOps CtrlALUOp = 5'd15;//LEQ from ALUOps
end else if (op == (REGIMM & (rt == (BLTZ | BLTZAL))))begin end else if ((op == REGIMM & ((rt == BLTZ | rt == BLTZAL))))begin
CtrlALUOp = 5'd14;//LES from ALUOps CtrlALUOp = 5'd14;//LES from ALUOps
end else if (OP == BNE)begin end else if (op == BNE)begin
CtrlALUOp = 5'd18;//NEQ from ALUOps CtrlALUOp = 5'd18;//NEQ from ALUOps
end else if (op == (SPECIAL & (funct == DIV)))begin end else if ((op == SPECIAL & (funct == DIV)))begin
CtrlALUOp = 5'd3;//DIV from ALUOps CtrlALUOp = 5'd3;//DIV from ALUOps
end else if (op == (SPECIAL & (funct == DIVU)))begin end else if ((op == SPECIAL & (funct == DIVU)))begin
CtrlALUOp = 5'd23;//DIVU from ALUOps CtrlALUOp = 5'd23;//DIVU from ALUOps
end else if (op == (LB | LBU | LH | LHU | LW | LWL | LWR | SB | SBH | SW))begin end else if ((op == LB | op == LBU | op == LH | op == LHU | op == LW | op == LWL | op == LWR | op == SB | op == SH | op == SW))begin
CtrlALUOp = 5'd0;//ADD from ALUOps CtrlALUOp = 5'd0;//ADD from ALUOps
end else if (op == LUI)begin end else if (op == LUI)begin
CtrlALUOp = 5'd7;//SLL from ALUOps CtrlALUOp = 5'd7;//SLL from ALUOps
end else if (op == (SPECIAL & (funct == MTHI | MTLO)))begin end else if ((op == SPECIAL & (funct == MTHI | MTLO)))begin
CtrlALUOp = 5'd19;//PAS from ALUOps CtrlALUOp = 5'd19;//PAS from ALUOps
end else if (op == (SPECIAL & (funct == MULT)))begin end else if ((op == SPECIAL & (funct == MULT)))begin
CtrlALUOp = 5'd2;//MUL from ALUOps CtrlALUOp = 5'd2;//MUL from ALUOps
end else if (op == (SPECIAL & (funct == MULTU)))begin end else if ((op == SPECIAL & (funct == MULTU)))begin
CtrlALUOp = 5'd22;//MULU from ALUOps CtrlALUOp = 5'd22;//MULU from ALUOps
end else if (op == (ORI | (SPECIAL & (funct == OR))))begin end else if ((op == ORI | (op == SPECIAL & (funct == OR))))begin
CtrlALUOp = 5'd5;//OR from ALUOps CtrlALUOp = 5'd5;//OR from ALUOps
end else if (op == (SPECIAL & (funct == SLL)))begin end else if (op == SPECIAL & (funct == SLL))begin
CtrlALUOp = 5'd7;//SLL from ALUOps CtrlALUOp = 5'd7;//SLL from ALUOps
end else if (op == (SPECIAL & (funct == SLLV)))begin end else if (op == SPECIAL & (funct == SLLV))begin
CtrlALUOp = 5'd8;//SLLV from ALUOps CtrlALUOp = 5'd8;//SLLV from ALUOps
end else if (op == (SPECIAL & (funct == SRA)))begin end else if (op == SPECIAL & (funct == SRA))begin
CtrlALUOp = 5'd11;//SRA from ALUOps CtrlALUOp = 5'd11;//SRA from ALUOps
end else if (op == (SPECIAL & (funct == SRAV)))begin end else if (op == SPECIAL & (funct == SRAV))begin
CtrlALUOp = 5'd12;//SRAV from ALUOps CtrlALUOp = 5'd12;//SRAV from ALUOps
end else if (op == (SPECIAL & (funct == SRL)))begin end else if (op == SPECIAL & (funct == SRL))begin
CtrlALUOp = 5'd9;//SRL from ALUOps CtrlALUOp = 5'd9;//SRL from ALUOps
end else if (op == (SPECIAL & (funct == SRLV)))begin end else if (op == SPECIAL & (funct == SRLV))begin
CtrlALUOp = 5'd10;//SRLV from ALUOps CtrlALUOp = 5'd10;//SRLV from ALUOps
end else if (op == (SLTI | (SPECIAL & (funct == SLT))))begin end else if (op == SLTI | (op == SPECIAL & (funct == SLT)))begin
CtrlALUOp = 5'd20;//SLT from ALUOps CtrlALUOp = 5'd20;//SLT from ALUOps
end else if (op == (SLTIU | (SPECIAL & (funct == SLTU))))begin end else if (op == SLTIU | (op == SPECIAL & (funct == SLTU)))begin
CtrlALUOp = 5'd21;//SLTU from ALUOps CtrlALUOp = 5'd21;//SLTU from ALUOps
end else if (op == (SPECIAL & (funct == SUBU)))begin end else if (op == SPECIAL & (funct == SUBU))begin
CtrlALUOp = 5'd1;//SUB from ALUOps CtrlALUOp = 5'd1;//SUB from ALUOps
end else if (op == (XORI | (SPECIAL & (funct == XOR))))begin end else if (op == XORI | (op == SPECIAL & (funct == XOR)))begin
CtrlALUOp = 5'd6;//XOR from ALUOps CtrlALUOp = 5'd6;//XOR from ALUOps
end else begin end else begin
CtrlALUOp = 5'bxxxxx; CtrlALUOp = 5'bxxxxx;
end end
//Ctrlshamt logic //Ctrlshamt logic
if(op == (SPECIAL & (funct == (SRA | SRL | SLL))))begin if(op == SPECIAL & (funct == (SRA | SRL | SLL)))begin
Ctrlshamt = Instr[10:6];// Shift amount piped in from the instruction Ctrlshamt = Instr[10:6];// Shift amount piped in from the instruction
end else if(op == LUI)begin end else if(op == LUI)begin
Ctrlshamt = 5'd16;//Used specifically to implement LUI as the instruction itslef does not include shamt Ctrlshamt = 5'd16;//Used specifically to implement LUI as the instruction itslef does not include shamt
end else begin Ctrlshamt = 5'bxxxxx;end end else begin Ctrlshamt = 5'bxxxxx;end
//CtrlMemWrite logic //CtrlMemWrite logic
if(op == (SB | SH | SW))begin if(op == SB | op == SH | op == SW)begin
CtrlMemWrite = 1;//Memory is write enabled CtrlMemWrite = 1;//Memory is write enabled
end else begin CtrlMemWrite = 0;end//default is 0 to ensure no accidental overwriting. end else begin CtrlMemWrite = 0;end//default is 0 to ensure no accidental overwriting.
//CtrlALUSrc logic //CtrlALUSrc logic
if(op == (ADDIU | ANDI | LUI | ORI | SLTI | SLTIU | XORI | LB | LBU | LH | LHU | LW | LWL | LWR | SB | SH | SW))begin if((op == ADDIU | op == ANDI | op == LUI | op == ORI | op == SLTI | op == SLTIU | op == XORI | op == LB | op == LBU | op == LH | op == LHU | op == LW | op == LWL | op == LWR | op == SB | op == SH | op == SW))begin
CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0] CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0]
end else if (op == (BEQ | BGTZ | BLEZ | BNE | (REGIMM & (rt == (BGEZ | BGEZAL | BLTZ | BLTZAL))) | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MULT | MULTU | OR | SLLV | SLT | SLTU | SRAV | SRLV | SUBU | XOR)))))begin end else if ((op == BEQ | op == BGTZ | op == BLEZ | op == BNE | (op == REGIMM & ((rt == BGEZ | rt == BGEZAL | rt == BLTZ | rt == BLTZAL))) | (op == SPECIAL & ((funct == ADDU | funct == AND | funct == DIV | funct == DIVU | funct == MULT | funct == MULTU | funct == OR | funct == SLLV | funct == SLT | funct == SLTU | funct == SRAV | funct == SRLV | funct == SUBU | funct == XOR)))))begin
CtrlALUSrc = 0;///ALU Bus B is fed from rt. CtrlALUSrc = 0;///ALU Bus B is fed from rt.
end else begin CtrlALUSrc = 1'bx;end end else begin CtrlALUSrc = 1'bx;end
//CtrlRegWrite logic //CtrlRegWrite logic
if(op == (ADDIU | ANDI | LB | LBU | LH | LHU | LUI | LW | LWL | LWR | ORI | SLTI | SLTIU | XORI | (SPECIAL & (funct == (ADDU | AND | DIV | DIVU | MULT | MULTU | JALR | OR | SLL | SLLV | SLT | SLTU | SRA | SRAV | SRL | SRLV | SUBU | XOR)))))begin if((op == ADDIU | op == ANDI | op == LB | op == LBU | op == LH | op == LHU | op == LUI | op == LW | op == LWL | op == LWR | op == ORI | op == SLTI | op == SLTIU | op == XORI | (op == SPECIAL & ((funct == ADDU | funct == AND | funct == DIV | funct == DIVU | funct == MULT | funct == MULTU | funct == JALR | funct == OR | funct == SLL | funct == SLLV | funct == SLT | funct == SLTU | funct == SRA | funct == SRAV | funct == SRL | funct == SRLV | funct == SUBU | funct == XOR)))))begin
CtrlRegWrite = 1;//The Registers are Write Enabled CtrlRegWrite = 1;//The Registers are Write Enabled
end else begin CtrlRegWrite = 0; end // The Registers are Write Disabled end else begin CtrlRegWrite = 0; end // The Registers are Write Disabled

27
rtl/mips_cpu_memory.v
View file

@ -31,36 +31,34 @@ module mips_cpu_memory(
); );
parameter RAM_INIT_FILE = ""; parameter RAM_INIT_FILE = "";
reg [31:0] memory [4294967295:0]; // 2^32 memory locations of 32 bits size reg [31:0] memory [0:7]; // 2^30 set as 8 for now for small testcases
initial begin initial begin
integer i; integer i;
//Initialise to zero by default //Initialise to zero by default
for (i=0; i<4294967296; i++) begin for (i=0; i<8; i++) begin
memory[i]=0; memory[i]=0;
end end
//Load contents from file if specified //Load contents from file if specified
if (RAM_INIT_FILE != "") begin if (RAM_INIT_FILE != "") begin
$display("RAM : INIT : Loading RAM contents from %s", RAM_INIT_FILE); $display("RAM: Loading RAM contents from %s", RAM_INIT_FILE);
$readmemh(RAM_INIT_FILE, memory, 32'hBFC00000, 32'd0); $readmemh(RAM_INIT_FILE, memory, 32'h4); //32'hBFC00000 equivalent for small memory as byte 16
end
//Display what's in memory for debugging
for (integer j = 0; j<$size(memory); j++) begin
$display("Byte %d, %h", j*4, memory[j]);
end end
end end
//Combinatorial read path for data and instruction. //Combinatorial read path for data and instruction.
always_comb begin assign data_readdata = data_read ? {memory[data_address],memory[data_address+1],memory[data_address+2],memory[data_address+3]} : 16'hxxxx;
if (clk == 1'd1) begin assign instr_readdata = memory[instr_address/4];
data_readdata = data_read ? memory[data_address] : 16'hxxxx;
instr_readdata = memory[instr_address];
end
else begin
data_readdata = data_readdata;
instr_readdata = instr_address;
end
end
//Synchronous write path //Synchronous write path
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
$display("Instruction Read: %h", instr_readdata);
//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]); //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
if (!data_read & data_write) begin //cannot read and write to memory in the same cycle if (!data_read & data_write) begin //cannot read and write to memory in the same cycle
if (instr_address != data_address) begin //cannot modify the instruction being read if (instr_address != data_address) begin //cannot modify the instruction being read
@ -70,3 +68,4 @@ module mips_cpu_memory(
end end
endmodule endmodule

37
test/test_mips_cpu_harvard.sh
View file

@ -23,41 +23,30 @@ echo ${INSTR};
if [[ ${INSTR} == "No instruction specified: running all testcases" ]]; if [[ ${INSTR} == "No instruction specified: running all testcases" ]];
then then
# All Testcase Files # All Testcase Files
TESTCASES=$(ls ./inputs | grep ".hex.txt"); TESTCASES=$(ls ./inputs | grep ".txt");
echo ${TESTCASES} echo ${TESTCASES}
for TESTCASE in ${TESTCASES} for TESTCASE in ${TESTCASES}
do do
# Run Each Testcase File # Run Each Testcase File
echo ${TESTCASE} echo ${TESTCASE}
#iverilog -g 2012 \ /mnt/c/Windows/System32/cmd.exe /C \
# -s mips_cpu_harvard_tb \ iverilog -Wall -g2012 \
# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/"${TESTCASE}\" \ -s mips_cpu_harvard_tb \
# -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \ -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${TESTCASE}.txt\" \
# ${SRC} -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \
${SRC}
/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${TESTCASE};
done done
else else
echo ${INSTR};
# Run Testcase File Of Specified Instruction # Run Testcase File Of Specified Instruction
# Windows Iverilog with WSL echo ${INSTR};
#/mnt/c/Windows/System32/cmd.exe /C iverilog -g2012 \ /mnt/c/Windows/System32/cmd.exe /C \
# -s mips_cpu_harvard_tb \ iverilog -Wall -g2012 \
# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
# -o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
# ${SRC}
# Linux Iverilog
iverilog -g2012 \
-s mips_cpu_harvard_tb \ -s mips_cpu_harvard_tb \
-P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \ -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/${INSTR}.txt\" \
-o program/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \ -o exec/mips_cpu_harvard_tb_${INSTR} testbench/mips_cpu_harvard_tb.v \
${SRC} ${SRC}
/mnt/c/Windows/System32/cmd.exe /C vvp ./exec/mips_cpu_harvard_tb_${INSTR};
fi fi
#/mnt/c/Windows/System32/cmd.exe /C \ # need this to run verilog on windows
#iverilog -g 2012 \
# -s mips_cpu_harvard_tb \
# -P mips_cpu_harvard_tb.RAM_INIT_FILE=\"inputs/addiu.hex.txt\" \
# -o program/mips_cpu_harvard_tb testbench/mips_cpu_harvard_tb.v test/mips_cpu_harvard.v \
# test/mips_cpu_control.v test/mips_cpu_alu.v test/mips_cpu_memory.v test/mips_cpu_regfile.v test/mips_cpu_pc.v

23
testbench/mips_cpu_harvard_tb.v
View file

@ -1,14 +1,10 @@
module mips_cpu_harvard_tb; module mips_cpu_harvard_tb;
timeunit 1ns / 10ps;
parameter RAM_INIT_FILE = "inputs/"; parameter RAM_INIT_FILE = "inputs/addu.txt";
parameter TIMEOUT_CYCLES = 10000; parameter TIMEOUT_CYCLES = 100;
logic clk, clk_enable, reset, active; logic clk, clk_enable, reset, active, data_read, data_write;
logic[31:0] register_v0; logic[31:0] register_v0, instr_address, instr_readdata, data_readdata, data_writedata, data_address;
logic[31:0] instr_address, instr_readdata;
logic data_read, data_write;
logic[31:0] data_readdata, data_writedata, data_address;
mips_cpu_memory #(RAM_INIT_FILE) ramInst( mips_cpu_memory #(RAM_INIT_FILE) ramInst(
.clk(clk), .clk(clk),
@ -50,24 +46,29 @@ module mips_cpu_harvard_tb;
end end
initial begin initial begin
$display("Initial Reset 0");
reset <= 0; reset <= 0;
$display("Initial Reset 1");
@(posedge clk); @(posedge clk);
reset <= 1; reset <= 1;
$display("Initial Reset 0: Start Program");
@(posedge clk); @(posedge clk);
reset <= 0; reset <= 0;
@(posedge clk); @(posedge clk);
assert(active==1) // Is this assert still valid? assert(active==1);
else $display("TB: CPU did not set active=1 after reset."); else $display("TB: CPU did not set active=1 after reset.");
while (active) begin while (active) begin
@(posedge clk); @(posedge clk);
$display("Register v0: %d", register_v0);
end end
$display("TB : finished; running=0"); $display("TB: finished; active=0");
$display("%d",register_v0); $display("Output: %d", register_v0);
$finish; $finish;
end end