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Use base+offset[1:0] for partial loads instead of base[1:0]

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Aadi Desai 2020-12-19 10:22:44 +00:00 committed by GitHub
parent 6797fc5a32
commit a598321539
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1 changed files with 8 additions and 7 deletions
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15
rtl/mips_cpu_regfile.v
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@ -8,6 +8,7 @@ input logic regwrite, //enable line for write port
input[5:0] opcode, //opcode input for controlling partial load weirdness input[5:0] opcode, //opcode input for controlling partial load weirdness
output logic[31:0] readdata1, //read port 1 output output logic[31:0] readdata1, //read port 1 output
output logic[31:0] readdata2, //read port 2 output output logic[31:0] readdata2, //read port 2 output
input logic[1:0] vaddr, //partial read offset from ALUout
output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results) output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results)
); );
@ -31,7 +32,7 @@ always_ff @(negedge clk) begin
end else if (regwrite) begin end else if (regwrite) begin
case (opcode) case (opcode)
6'b100000: begin //lb, load byte 6'b100000: begin //lb, load byte
case (readdata1[1:0]) case (vaddr)
2'b00: memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]}; 2'b00: memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]};
2'b01: memory[writereg] <= {{24{writedata[15]}}, writedata[15:8]}; 2'b01: memory[writereg] <= {{24{writedata[15]}}, writedata[15:8]};
2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]}; 2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]};
@ -39,7 +40,7 @@ always_ff @(negedge clk) begin
endcase // readdata1[1:0] endcase // readdata1[1:0]
end end
6'b100100: begin //lbu, load byte unsigned 6'b100100: begin //lbu, load byte unsigned
case (readdata1[1:0]) case (vaddr)
2'b00: memory[writereg] <= {{24{1'b0}}, writedata[7:0]}; 2'b00: memory[writereg] <= {{24{1'b0}}, writedata[7:0]};
2'b01: memory[writereg] <= {{24{1'b0}}, writedata[15:8]}; 2'b01: memory[writereg] <= {{24{1'b0}}, writedata[15:8]};
2'b10: memory[writereg] <= {{24{1'b0}}, writedata[23:16]}; 2'b10: memory[writereg] <= {{24{1'b0}}, writedata[23:16]};
@ -47,19 +48,19 @@ always_ff @(negedge clk) begin
endcase // readdata1[1:0] endcase // readdata1[1:0]
end end
6'b100001: begin //lh, load half-word 6'b100001: begin //lh, load half-word
case (readdata1[1:0]) // must be half-word aligned, readdata1[0] = 0 case (vaddr]) // must be half-word aligned, readdata1[0] = 0
2'b00: memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]}; 2'b00: memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]};
2'b10: memory[writereg] <= {{16{writedata[31]}}, writedata[31:16]}; 2'b10: memory[writereg] <= {{16{writedata[31]}}, writedata[31:16]};
endcase // readdata1[1:0] endcase // readdata1[1:0]
end end
6'b100101: begin //lhu, load half-word unsigned 6'b100101: begin //lhu, load half-word unsigned
case (readdata1[1:0]) // must be half-word aligned, readdata1[0] = 0 case (vaddr) // must be half-word aligned, readdata1[0] = 0
2'b00: memory[writereg] <= {{16{1'b0}}, writedata[15:0]}; 2'b00: memory[writereg] <= {{16{1'b0}}, writedata[15:0]};
2'b10: memory[writereg] <= {{16{1'b0}}, writedata[31:16]}; 2'b10: memory[writereg] <= {{16{1'b0}}, writedata[31:16]};
endcase // readdata1[1:0] endcase // readdata1[1:0]
end end
6'b100010: begin //lwl, load word left 6'b100010: begin //lwl, load word left
case (readdata1[1:0]) case (vaddr)
2'b00: memory[writereg][31:24] <= writedata[7:0]; 2'b00: memory[writereg][31:24] <= writedata[7:0];
2'b01: memory[writereg][31:16] <= writedata[15:0]; 2'b01: memory[writereg][31:16] <= writedata[15:0];
2'b10: memory[writereg][31:8] <= writedata[23:0]; 2'b10: memory[writereg][31:8] <= writedata[23:0];
@ -67,7 +68,7 @@ always_ff @(negedge clk) begin
endcase // readdata1[1:0] endcase // readdata1[1:0]
end end
6'b100110: begin //lwr, load word right 6'b100110: begin //lwr, load word right
case (readdata1[1:0]) case (vaddr)
2'b00: memory[writereg][31:0] <= writedata[31:0]; 2'b00: memory[writereg][31:0] <= writedata[31:0];
2'b01: memory[writereg][23:0] <= writedata[31:8]; 2'b01: memory[writereg][23:0] <= writedata[31:8];
2'b10: memory[writereg][15:0] <= writedata[31:16]; 2'b10: memory[writereg][15:0] <= writedata[31:16];
@ -81,4 +82,4 @@ always_ff @(negedge clk) begin
end end
end end
endmodule endmodule