diff --git a/rtl/mips_cpu_regfile.v b/rtl/mips_cpu_regfile.v
index 6d27df6..968632a 100644
--- a/rtl/mips_cpu_regfile.v
+++ b/rtl/mips_cpu_regfile.v
@@ -8,6 +8,7 @@ input logic regwrite, //enable line for write port
 input[5:0] opcode, //opcode input for controlling partial load weirdness
 output logic[31:0] readdata1, //read port 1 output
 output logic[31:0] readdata2, //read port 2 output
+input logic[1:0] vaddr, //partial read offset from ALUout
 output logic[31:0] regv0 //debug output of $v0 or $2 (third register in file/ first register for returning function results)
 );
 
@@ -31,7 +32,7 @@ always_ff @(negedge clk) begin
 	end else if (regwrite) begin
 		case (opcode)
 			6'b100000: begin //lb, load byte
-				case (readdata1[1:0])	
+				case (vaddr)	
 					2'b00: memory[writereg] <= {{24{writedata[7]}}, writedata[7:0]};
 					2'b01: memory[writereg] <= {{24{writedata[15]}}, writedata[15:8]};
 					2'b10: memory[writereg] <= {{24{writedata[23]}}, writedata[23:16]};
@@ -39,7 +40,7 @@ always_ff @(negedge clk) begin
 				endcase // readdata1[1:0]
 			end
 			6'b100100: begin //lbu, load byte unsigned
-				case (readdata1[1:0])
+				case (vaddr)
 					2'b00: memory[writereg] <= {{24{1'b0}}, writedata[7:0]};
 					2'b01: memory[writereg] <= {{24{1'b0}}, writedata[15:8]};
 					2'b10: memory[writereg] <= {{24{1'b0}}, writedata[23:16]};
@@ -47,19 +48,19 @@ always_ff @(negedge clk) begin
 				endcase // readdata1[1:0]
 			end
 			6'b100001: begin //lh, load half-word
-				case (readdata1[1:0]) // must be half-word aligned, readdata1[0] = 0
+				case (vaddr]) // must be half-word aligned, readdata1[0] = 0
 					2'b00: memory[writereg] <= {{16{writedata[15]}}, writedata[15:0]};
 					2'b10: memory[writereg] <= {{16{writedata[31]}}, writedata[31:16]};
 				endcase // readdata1[1:0]
 			end
 			6'b100101: begin //lhu, load half-word unsigned
-				case (readdata1[1:0]) // must be half-word aligned, readdata1[0] = 0
+				case (vaddr) // must be half-word aligned, readdata1[0] = 0
 					2'b00: memory[writereg] <= {{16{1'b0}}, writedata[15:0]};
 					2'b10: memory[writereg] <= {{16{1'b0}}, writedata[31:16]};
 				endcase // readdata1[1:0]
 			end
 			6'b100010: begin //lwl, load word left
-				case (readdata1[1:0])
+				case (vaddr)
 					2'b00: memory[writereg][31:24] <= writedata[7:0];
 					2'b01: memory[writereg][31:16] <= writedata[15:0];
 					2'b10: memory[writereg][31:8] <= writedata[23:0];
@@ -67,7 +68,7 @@ always_ff @(negedge clk) begin
 				endcase // readdata1[1:0]
 			end
 			6'b100110: begin //lwr, load word right
-				case (readdata1[1:0])
+				case (vaddr)
 					2'b00: memory[writereg][31:0] <= writedata[31:0];
 					2'b01: memory[writereg][23:0] <= writedata[31:8];
 					2'b10: memory[writereg][15:0] <= writedata[31:16];
@@ -81,4 +82,4 @@ always_ff @(negedge clk) begin
 	end
 end
 
-endmodule
\ No newline at end of file
+endmodule