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Ibrahim 2020-12-02 14:32:42 +00:00
parent 888bb7c822
commit a56410ceae
1 changed files with 8 additions and 11 deletions
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19
rtl/mips_cpu_alu.v
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@ -9,13 +9,10 @@ module mips_cpu_alu(
output logic[31:0] ALUOut, // The ouput of the ALU output logic[31:0] ALUOut, // The ouput of the ALU
input logic[15:0] immediate,
input logic[4:0] shamt input logic[4:0] shamt
); );
input [15:0] immediate;
reg [31:0] SignExtend, ZeroExtend; reg [31:0] SignExtend, ZeroExtend;
// Instructions commented out have been accounted for // Instructions commented out have been accounted for
@ -139,38 +136,38 @@ module mips_cpu_alu(
BGEZ: begin BGEZ: begin
if A>=0 begin if A>=0 begin
ALUOut = 0; Cond = 1;
end end
else begin else begin
ALUOut = ALUOut; Cond = 0;
end end
end end
BGEZAL: begin BGEZAL: begin
if A>=0 begin if A>=0 begin
ALUOut = 0; Cond = 1;
end end
else begin else begin
ALUOut = ALUOut; Cond = 0;
end end
end end
BGTZ: begin BGTZ: begin
if A>0 begin if A>0 begin
ALUOut = 0; Cond = 1;
end end
else begin else begin
ALUOut = ALUOut; Cond = 0;
end end
end end
BLEZ: begin BLEZ: begin
if A<=0 begin if A<=0 begin
ALUOut = 0; Cond = 1;
end end
else begin else begin
ALUOut = ALUOut; Cond = 0;
end end
end end