mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-12-22 13:25:49 +00:00
Fix sltiu in control, sb/sh instr and add jr 31 instr
This commit is contained in:
parent
62c7ffc32b
commit
9003384106
4
inputs/addiu/addiu-3.instr.txt
Normal file
4
inputs/addiu/addiu-3.instr.txt
Normal file
|
@ -0,0 +1,4 @@
|
|||
25080000
|
||||
03e00008
|
||||
25080000
|
||||
00000000
|
1
inputs/addiu/addiu-3.ref.txt
Normal file
1
inputs/addiu/addiu-3.ref.txt
Normal file
|
@ -0,0 +1 @@
|
|||
0
|
|
@ -1,5 +1,5 @@
|
|||
3C041234
|
||||
34045678
|
||||
34845678
|
||||
3405101C
|
||||
A0A40000
|
||||
80A20000
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
3C041234
|
||||
34045678
|
||||
34845678
|
||||
3405101C
|
||||
A0A40000
|
||||
8CA20000
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
3C041234
|
||||
34045678
|
||||
34845678
|
||||
3405101C
|
||||
A4A40000
|
||||
84A20000
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
3C041234
|
||||
34045678
|
||||
34845678
|
||||
3405101C
|
||||
A4A40000
|
||||
8CA20000
|
||||
|
|
|
@ -1 +1 @@
|
|||
0
|
||||
1
|
|
@ -207,7 +207,7 @@ always @(*) begin
|
|||
end else begin CtrlALUSrc = 1'bx;end
|
||||
|
||||
//CtrlRegWrite logic
|
||||
if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
|
||||
if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTIU) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
|
||||
CtrlRegWrite = 1;//The Registers are Write Enabled
|
||||
end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
|
||||
end
|
||||
|
|
Loading…
Reference in a new issue