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https://github.com/supleed2/ELEC50010-IAC-CW.git
synced 2024-12-22 21:35:48 +00:00
Fixed BGEZAL
This commit is contained in:
parent
2673e23137
commit
7185f7e7e6
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@ -1,5 +1,4 @@
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3C04FFFF
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3C04FFFF
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00000000
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04800003
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04800003
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00000000
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00000000
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00000008
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00000008
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@ -1,4 +1,4 @@
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3C05BCF0
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3C05BFC0
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34A5001C
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34A5001C
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00A02009
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00A02009
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00000000
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00000000
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@ -6,4 +6,4 @@
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00000008
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00000008
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00000000
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00000000
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34020001
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34020001
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00800008
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00800008
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@ -93,7 +93,7 @@ always @(*) begin
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end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin
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end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin
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CtrlRegDst = 2'd1; //Write address comes from rd
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CtrlRegDst = 2'd1; //Write address comes from rd
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$display("CTRLREGDST: Rd");
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$display("CTRLREGDST: Rd");
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end else if (op == JAL)begin
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end else if ((op == JAL) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin
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CtrlRegDst = 2'd2; //const reg 31, for writing to the link register
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CtrlRegDst = 2'd2; //const reg 31, for writing to the link register
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$display("CTRLREGDST: Link");
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$display("CTRLREGDST: Link");
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end else begin CtrlRegDst = 1'bx; $display("xxxxxxxxxxxxxx");end//Not all instructions are encompassed so, added incase for debug purposes
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end else begin CtrlRegDst = 1'bx; $display("xxxxxxxxxxxxxx");end//Not all instructions are encompassed so, added incase for debug purposes
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@ -118,7 +118,7 @@ always @(*) begin
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CtrlMemRead = 0;//Memory is read disabled
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CtrlMemRead = 0;//Memory is read disabled
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CtrlMemtoReg = 3'd0;//write data port of regfile is fed from ALURes
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CtrlMemtoReg = 3'd0;//write data port of regfile is fed from ALURes
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$display("Memory read disabled");
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$display("Memory read disabled");
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end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)))begin
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end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin
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CtrlMemtoReg = 3'd2;//write data port of regfile is fed from PC + 8
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CtrlMemtoReg = 3'd2;//write data port of regfile is fed from PC + 8
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end else if ((op==SPECIAL)&&(funct == MFHI))begin
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end else if ((op==SPECIAL)&&(funct == MFHI))begin
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CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi
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CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi
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@ -224,7 +224,7 @@ always @(*) begin
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end else begin CtrlALUSrc = 1'bx;end
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end else begin CtrlALUSrc = 1'bx;end
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//CtrlRegWrite logic
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//CtrlRegWrite logic
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if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
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if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
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CtrlRegWrite = 1;//The Registers are Write Enabled
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CtrlRegWrite = 1;//The Registers are Write Enabled
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$display("OPcode mflo: %h", op);
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$display("OPcode mflo: %h", op);
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end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
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end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
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@ -13,11 +13,11 @@ module mips_cpu_harvard(
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input logic[31:0] instr_readdata,//port from instruction memory out, going to various inputs.
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input logic[31:0] instr_readdata,//port from instruction memory out, going to various inputs.
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/* Combinatorial read and single-cycle write access to instructions */
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/* Combinatorial read and single-cycle write access to instructions */
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output logic[31:0] data_address,//Port from ALURes going into Data Memory 'Address' port
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output logic[31:0] data_address,
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output logic data_write,//Control line from 'control' CtrlMemWrite enabling/disabling write access for Data Memory.
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output logic data_write,
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output logic data_read,//Control line from 'control' CtrlMemRead enabling/disabling read access for Data Memory.
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output logic data_read,
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output logic[31:0] data_writedata,//Data from Register file 'Read data 2' port, aka rt's data, going to 'Write data' port on Data Memory.
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output logic[31:0] data_writedata,
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input logic[31:0] data_readdata//port from data memory out, going to the 'Write Register' port in regfile.
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input logic[31:0] data_readdata
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);
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);
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assign instr_address = out_pc_out;
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assign instr_address = out_pc_out;
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@ -61,6 +61,7 @@ always @(*) begin
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end
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end
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3'd2:begin
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3'd2:begin
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in_writedata = (out_pc_out + 32'd8);//Output from PC +8.
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in_writedata = (out_pc_out + 32'd8);//Output from PC +8.
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$display("LINKING-----------<: %h", in_writedata);
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end
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end
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3'd3:begin
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3'd3:begin
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in_writedata = (out_ALUHi);
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in_writedata = (out_ALUHi);
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@ -16,7 +16,7 @@ module mips_cpu_memory(
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parameter INSTR_INIT_FILE = "";
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parameter INSTR_INIT_FILE = "";
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parameter DATA_INIT_FILE = "";
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parameter DATA_INIT_FILE = "";
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reg [31:0] data_memory [0:31];
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reg [31:0] data_memory [0:31];
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reg [31:0] instr_memory [0:31];
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reg [31:0] instr_memory [0:63];
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initial begin
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initial begin
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integer i;
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integer i;
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