From 7185f7e7e6e750966131572a8b05593ae984aa43 Mon Sep 17 00:00:00 2001 From: Jeevaha Coelho Date: Wed, 16 Dec 2020 07:00:46 -0800 Subject: [PATCH] Fixed BGEZAL --- inputs/bltz/bltz-1.txt | 1 - inputs/jalr/jalr-1.txt | 4 ++-- rtl/mips_cpu_control.v | 6 +++--- rtl/mips_cpu_harvard.v | 11 ++++++----- rtl/mips_cpu_memory.v | 2 +- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/inputs/bltz/bltz-1.txt b/inputs/bltz/bltz-1.txt index 758b0d3..d4068af 100644 --- a/inputs/bltz/bltz-1.txt +++ b/inputs/bltz/bltz-1.txt @@ -1,5 +1,4 @@ 3C04FFFF -00000000 04800003 00000000 00000008 diff --git a/inputs/jalr/jalr-1.txt b/inputs/jalr/jalr-1.txt index 2c5bb1c..574ba5c 100644 --- a/inputs/jalr/jalr-1.txt +++ b/inputs/jalr/jalr-1.txt @@ -1,4 +1,4 @@ -3C05BCF0 +3C05BFC0 34A5001C 00A02009 00000000 @@ -6,4 +6,4 @@ 00000008 00000000 34020001 -00800008 \ No newline at end of file +00800008 diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v index b78c885..5ce988b 100644 --- a/rtl/mips_cpu_control.v +++ b/rtl/mips_cpu_control.v @@ -93,7 +93,7 @@ always @(*) begin end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin CtrlRegDst = 2'd1; //Write address comes from rd $display("CTRLREGDST: Rd"); - end else if (op == JAL)begin + end else if ((op == JAL) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin CtrlRegDst = 2'd2; //const reg 31, for writing to the link register $display("CTRLREGDST: Link"); end else begin CtrlRegDst = 1'bx; $display("xxxxxxxxxxxxxx");end//Not all instructions are encompassed so, added incase for debug purposes @@ -118,7 +118,7 @@ always @(*) begin CtrlMemRead = 0;//Memory is read disabled CtrlMemtoReg = 3'd0;//write data port of regfile is fed from ALURes $display("Memory read disabled"); - end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)))begin + end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin CtrlMemtoReg = 3'd2;//write data port of regfile is fed from PC + 8 end else if ((op==SPECIAL)&&(funct == MFHI))begin CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi @@ -224,7 +224,7 @@ always @(*) begin end else begin CtrlALUSrc = 1'bx;end //CtrlRegWrite logic - if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin + if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin CtrlRegWrite = 1;//The Registers are Write Enabled $display("OPcode mflo: %h", op); end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled diff --git a/rtl/mips_cpu_harvard.v b/rtl/mips_cpu_harvard.v index 3debd63..ae21b3c 100644 --- a/rtl/mips_cpu_harvard.v +++ b/rtl/mips_cpu_harvard.v @@ -13,11 +13,11 @@ module mips_cpu_harvard( input logic[31:0] instr_readdata,//port from instruction memory out, going to various inputs. /* Combinatorial read and single-cycle write access to instructions */ - output logic[31:0] data_address,//Port from ALURes going into Data Memory 'Address' port - output logic data_write,//Control line from 'control' CtrlMemWrite enabling/disabling write access for Data Memory. - output logic data_read,//Control line from 'control' CtrlMemRead enabling/disabling read access for Data Memory. - output logic[31:0] data_writedata,//Data from Register file 'Read data 2' port, aka rt's data, going to 'Write data' port on Data Memory. - input logic[31:0] data_readdata//port from data memory out, going to the 'Write Register' port in regfile. + output logic[31:0] data_address, + output logic data_write, + output logic data_read, + output logic[31:0] data_writedata, + input logic[31:0] data_readdata ); assign instr_address = out_pc_out; @@ -61,6 +61,7 @@ always @(*) begin end 3'd2:begin in_writedata = (out_pc_out + 32'd8);//Output from PC +8. + $display("LINKING-----------<: %h", in_writedata); end 3'd3:begin in_writedata = (out_ALUHi); diff --git a/rtl/mips_cpu_memory.v b/rtl/mips_cpu_memory.v index a3984a9..6582e50 100644 --- a/rtl/mips_cpu_memory.v +++ b/rtl/mips_cpu_memory.v @@ -16,7 +16,7 @@ module mips_cpu_memory( parameter INSTR_INIT_FILE = ""; parameter DATA_INIT_FILE = ""; reg [31:0] data_memory [0:31]; - reg [31:0] instr_memory [0:31]; + reg [31:0] instr_memory [0:63]; initial begin integer i;