Rename .v to .sv for Quartus to detect as SystemVerilog

2024-09-19 19:46:17 +00:00 · 2020-12-19 15:58:00 +00:00 · 2020-12-19 15:58:00 +00:00 · 6c0554538c
parent f56d61f2f3
commit 6c0554538c
12 changed files with 52 additions and 52 deletions
--- a/rtl/mips_cpu_alu.sv
+++ b/rtl/mips_cpu_alu.sv
--- a/rtl/mips_cpu_bus.sv
+++ b/rtl/mips_cpu_bus.sv
--- a/rtl/mips_cpu_control.sv
+++ b/rtl/mips_cpu_control.sv
--- a/rtl/mips_cpu_cpc.sv
+++ b/rtl/mips_cpu_cpc.sv
--- a/rtl/mips_cpu_harvard.sv
+++ b/rtl/mips_cpu_harvard.sv
--- a/rtl/mips_cpu_npc.sv
+++ b/rtl/mips_cpu_npc.sv
--- a/rtl/mips_cpu_pc.sv
+++ b/rtl/mips_cpu_pc.sv
--- a/rtl/mips_cpu_regfile.sv
+++ b/rtl/mips_cpu_regfile.sv
--- a/testbench/mips_cpu_bus_memory.sv
+++ b/testbench/mips_cpu_bus_memory.sv
--- a/testbench/mips_cpu_bus_tb.sv
+++ b/testbench/mips_cpu_bus_tb.sv
--- a/testbench/mips_cpu_harvard_memory.sv
+++ b/testbench/mips_cpu_harvard_memory.sv
--- a/testbench/mips_cpu_harvard_tb.sv
+++ b/testbench/mips_cpu_harvard_tb.sv