From 6c0554538c27601e4c998eff27d5d1c456f0a1fe Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Sat, 19 Dec 2020 15:58:00 +0000
Subject: [PATCH] Rename .v to .sv for Quartus to detect as SystemVerilog

---
 rtl/{mips_cpu_alu.v => mips_cpu_alu.sv}       |   0
 rtl/{mips_cpu_bus.v => mips_cpu_bus.sv}       |   0
 ...mips_cpu_control.v => mips_cpu_control.sv} |   0
 rtl/{mips_cpu_cpc.v => mips_cpu_cpc.sv}       |   0
 ...mips_cpu_harvard.v => mips_cpu_harvard.sv} |   0
 rtl/{mips_cpu_npc.v => mips_cpu_npc.sv}       |   0
 rtl/{mips_cpu_pc.v => mips_cpu_pc.sv}         | 104 +++++++++---------
 ...mips_cpu_regfile.v => mips_cpu_regfile.sv} |   0
 ...pu_bus_memory.v => mips_cpu_bus_memory.sv} |   0
 .../{mips_cpu_bus_tb.v => mips_cpu_bus_tb.sv} |   0
 ...rd_memory.v => mips_cpu_harvard_memory.sv} |   0
 ...pu_harvard_tb.v => mips_cpu_harvard_tb.sv} |   0
 12 files changed, 52 insertions(+), 52 deletions(-)
 rename rtl/{mips_cpu_alu.v => mips_cpu_alu.sv} (100%)
 rename rtl/{mips_cpu_bus.v => mips_cpu_bus.sv} (100%)
 rename rtl/{mips_cpu_control.v => mips_cpu_control.sv} (100%)
 rename rtl/{mips_cpu_cpc.v => mips_cpu_cpc.sv} (100%)
 rename rtl/{mips_cpu_harvard.v => mips_cpu_harvard.sv} (100%)
 rename rtl/{mips_cpu_npc.v => mips_cpu_npc.sv} (100%)
 rename rtl/{mips_cpu_pc.v => mips_cpu_pc.sv} (95%)
 rename rtl/{mips_cpu_regfile.v => mips_cpu_regfile.sv} (100%)
 rename testbench/{mips_cpu_bus_memory.v => mips_cpu_bus_memory.sv} (100%)
 rename testbench/{mips_cpu_bus_tb.v => mips_cpu_bus_tb.sv} (100%)
 rename testbench/{mips_cpu_harvard_memory.v => mips_cpu_harvard_memory.sv} (100%)
 rename testbench/{mips_cpu_harvard_tb.v => mips_cpu_harvard_tb.sv} (100%)

diff --git a/rtl/mips_cpu_alu.v b/rtl/mips_cpu_alu.sv
similarity index 100%
rename from rtl/mips_cpu_alu.v
rename to rtl/mips_cpu_alu.sv
diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.sv
similarity index 100%
rename from rtl/mips_cpu_bus.v
rename to rtl/mips_cpu_bus.sv
diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.sv
similarity index 100%
rename from rtl/mips_cpu_control.v
rename to rtl/mips_cpu_control.sv
diff --git a/rtl/mips_cpu_cpc.v b/rtl/mips_cpu_cpc.sv
similarity index 100%
rename from rtl/mips_cpu_cpc.v
rename to rtl/mips_cpu_cpc.sv
diff --git a/rtl/mips_cpu_harvard.v b/rtl/mips_cpu_harvard.sv
similarity index 100%
rename from rtl/mips_cpu_harvard.v
rename to rtl/mips_cpu_harvard.sv
diff --git a/rtl/mips_cpu_npc.v b/rtl/mips_cpu_npc.sv
similarity index 100%
rename from rtl/mips_cpu_npc.v
rename to rtl/mips_cpu_npc.sv
diff --git a/rtl/mips_cpu_pc.v b/rtl/mips_cpu_pc.sv
similarity index 95%
rename from rtl/mips_cpu_pc.v
rename to rtl/mips_cpu_pc.sv
index fad1b8c..bf47e90 100644
--- a/rtl/mips_cpu_pc.v
+++ b/rtl/mips_cpu_pc.sv
@@ -1,53 +1,53 @@
-module mips_cpu_pc(
-input logic clk,
-input logic rst,
-input logic[31:0] Instr,
-input logic[31:0] JumpReg,
-input logic[1:0] pc_ctrl,
-output logic[31:0] pc_out,
-output logic active
-);
-
-logic[31:0] out_cpc_out;
-logic[31:0] out_npc_out;
-logic[31:0] in_npc_in;
-
-assign pc_out = out_cpc_out;
-
-always @(*) begin
-    case(pc_ctrl)
-        2'd0: begin
-            in_npc_in = out_npc_out + 32'd4;//No branch or jump or load.
-        end
-        2'd1: begin
-            in_npc_in = out_npc_out + {{14{Instr[15]}}, Instr[15:0], 2'b00};
-        end
-        2'd2: begin
-            in_npc_in = {out_npc_out[31:28], Instr[25:0], 2'b00};
-        end
-        2'd3: begin
-            in_npc_in = JumpReg;
-        end
-    endcase	
-end
-
-mips_cpu_cpc cpc(
-//Inputs for cpc
-	.clk(clk),
-	.rst(rst),
-	.cpc_in(out_npc_out),
-//Outputs for cpc
-	.cpc_out(out_cpc_out),
-    .active(active)
-);
-
-mips_cpu_npc npc(
-//Inputs for npc
-	.clk(clk),
-	.rst(rst),
-	.npc_in(in_npc_in),
-//Outputs for npc
-	.npc_out(out_npc_out)
-);
-
+module mips_cpu_pc(
+input logic clk,
+input logic rst,
+input logic[31:0] Instr,
+input logic[31:0] JumpReg,
+input logic[1:0] pc_ctrl,
+output logic[31:0] pc_out,
+output logic active
+);
+
+logic[31:0] out_cpc_out;
+logic[31:0] out_npc_out;
+logic[31:0] in_npc_in;
+
+assign pc_out = out_cpc_out;
+
+always @(*) begin
+    case(pc_ctrl)
+        2'd0: begin
+            in_npc_in = out_npc_out + 32'd4;//No branch or jump or load.
+        end
+        2'd1: begin
+            in_npc_in = out_npc_out + {{14{Instr[15]}}, Instr[15:0], 2'b00};
+        end
+        2'd2: begin
+            in_npc_in = {out_npc_out[31:28], Instr[25:0], 2'b00};
+        end
+        2'd3: begin
+            in_npc_in = JumpReg;
+        end
+    endcase	
+end
+
+mips_cpu_cpc cpc(
+//Inputs for cpc
+	.clk(clk),
+	.rst(rst),
+	.cpc_in(out_npc_out),
+//Outputs for cpc
+	.cpc_out(out_cpc_out),
+    .active(active)
+);
+
+mips_cpu_npc npc(
+//Inputs for npc
+	.clk(clk),
+	.rst(rst),
+	.npc_in(in_npc_in),
+//Outputs for npc
+	.npc_out(out_npc_out)
+);
+
 endmodule
\ No newline at end of file
diff --git a/rtl/mips_cpu_regfile.v b/rtl/mips_cpu_regfile.sv
similarity index 100%
rename from rtl/mips_cpu_regfile.v
rename to rtl/mips_cpu_regfile.sv
diff --git a/testbench/mips_cpu_bus_memory.v b/testbench/mips_cpu_bus_memory.sv
similarity index 100%
rename from testbench/mips_cpu_bus_memory.v
rename to testbench/mips_cpu_bus_memory.sv
diff --git a/testbench/mips_cpu_bus_tb.v b/testbench/mips_cpu_bus_tb.sv
similarity index 100%
rename from testbench/mips_cpu_bus_tb.v
rename to testbench/mips_cpu_bus_tb.sv
diff --git a/testbench/mips_cpu_harvard_memory.v b/testbench/mips_cpu_harvard_memory.sv
similarity index 100%
rename from testbench/mips_cpu_harvard_memory.v
rename to testbench/mips_cpu_harvard_memory.sv
diff --git a/testbench/mips_cpu_harvard_tb.v b/testbench/mips_cpu_harvard_tb.sv
similarity index 100%
rename from testbench/mips_cpu_harvard_tb.v
rename to testbench/mips_cpu_harvard_tb.sv