FIxed PC!

This commit is contained in:
Jeevaha Coelho 2020-12-16 05:21:57 -08:00
parent ad68ab0974
commit 2673e23137
6 changed files with 111 additions and 52 deletions

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@ -1 +1 @@
4 15

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@ -114,7 +114,7 @@ always @(*) begin
CtrlMemRead = 1;//Memory is read enabled CtrlMemRead = 1;//Memory is read enabled
CtrlMemtoReg = 3'd1;//write data port of regfile is fed from data memory CtrlMemtoReg = 3'd1;//write data port of regfile is fed from data memory
$display("Memory read enabled"); $display("Memory read enabled");
end else if ((op==ADDIU) || (op==ANDI) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))))begin end else if ((op==ADDIU) || (op==ANDI) || (op==ORI) || (op==LUI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))))begin
CtrlMemRead = 0;//Memory is read disabled CtrlMemRead = 0;//Memory is read disabled
CtrlMemtoReg = 3'd0;//write data port of regfile is fed from ALURes CtrlMemtoReg = 3'd0;//write data port of regfile is fed from ALURes
$display("Memory read disabled"); $display("Memory read disabled");

35
rtl/mips_cpu_cpc.v Normal file
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@ -0,0 +1,35 @@
module mips_cpu_cpc(
input logic clk,
input logic rst,
input logic[31:0] cpc_in,
output logic[31:0] cpc_out,
output logic active
);
reg[31:0] cpc_curr;
reg is_active;
initial begin
cpc_curr = 32'hBFC00000;
end // initial
always_comb begin
if (rst) begin
cpc_curr = 32'hBFC00000;
is_active = 1;
end else begin
cpc_curr = cpc_in;
end
if(cpc_in == 32'd0)begin
is_active = 0;
end
end
always_ff @(posedge clk) begin
cpc_out <= cpc_curr;
active <= is_active;
end
endmodule // pc

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@ -88,8 +88,8 @@ mips_cpu_pc pc(
//PC inputs //PC inputs
.clk(clk),//clk taken from the Standard signals .clk(clk),//clk taken from the Standard signals
.rst(reset),//clk taken from the Standard signals .rst(reset),//clk taken from the Standard signals
.instr(instr_readdata), //needed for branches and jumps .Instr(instr_readdata), //needed for branches and jumps
.reg_readdata(out_readdata1), //needed for jump register .JumpReg(out_readdata1), //needed for jump register
.pc_ctrl(out_PC), .pc_ctrl(out_PC),
//PC outputs //PC outputs
.pc_out(out_pc_out),//What the pc outputs at every clock edge that goes into the 'Read address' port of Instruction Memory. .pc_out(out_pc_out),//What the pc outputs at every clock edge that goes into the 'Read address' port of Instruction Memory.

27
rtl/mips_cpu_npc.v Normal file
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@ -0,0 +1,27 @@
module mips_cpu_npc(
input logic clk,
input logic rst,
input logic[31:0] npc_in,
output logic[31:0] npc_out
);
reg[31:0] npc_curr;
initial begin
npc_curr = (32'hBFC00000 + 32'd4);
end // initial
always_comb begin
if (rst) begin
npc_curr = (32'hBFC00000 + 32'd4);
end else begin
npc_curr = npc_in;
end
end
always_ff @(posedge clk) begin
npc_out <= npc_curr;
end
endmodule // pc

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@ -1,56 +1,53 @@
module mips_cpu_pc( module mips_cpu_pc(
input logic clk, input logic clk,
input logic rst, input logic rst,
input logic[1:0] pc_ctrl, input logic[31:0] Instr,
input logic[31:0] instr, input logic[31:0] JumpReg,
input logic[31:0] reg_readdata, input logic[1:0] pc_ctrl,
output logic[31:0] pc_out, output logic[31:0] pc_out,
output logic active output logic active
); );
reg [31:0] pc_next, pc_lit_next, pc_next_next; logic[31:0] out_cpc_out;
logic[31:0] out_npc_out;
logic[31:0] in_npc_in;
initial begin assign pc_out = out_cpc_out;
pc_out = 32'hBFC00000;
pc_next = pc_out + 32'd4;
end
assign pc_lit_next = pc_out + 32'd4;
always_ff @(posedge clk) begin
if (rst) begin
active <= 1;
pc_out <= 32'hBFC00000;
end else begin
if(pc_out == 32'd0) begin
active <= 0;
end
pc_out <= pc_next;
pc_next <= pc_next_next;
end
end
always @(*) begin always @(*) begin
case(pc_ctrl) case(pc_ctrl)
2'd1: begin // Branch 2'd0: begin
pc_next_next = pc_out + 32'd4 + {{14{instr[15]}},instr[15:0],2'b00}; in_npc_in = out_npc_out + 32'd4;//No branch or jump or load.
end end
2'd2: begin // Jump 2'd1: begin
pc_next_next = {pc_lit_next[31:28], instr[25:0], 2'b00}; in_npc_in = out_npc_out + {{14{Instr[15]}}, Instr[15:0], 2'b00};
$display("JUMPING");
$display("pc_lit_next: %h", pc_lit_next[31:28]);
$display("instr: %b", instr[25:0]);
$display("%h",pc_next);
end end
2'd3: begin // Jump using Register 2'd2: begin
pc_next_next = reg_readdata; in_npc_in = {out_npc_out[31:28], Instr[25:0], 2'b00};
$display("REGREADEADTAATATAT %h", reg_readdata);
end end
default: begin 2'd3: begin
pc_next_next = pc_out + 32'd4; in_npc_in = JumpReg;
end end
endcase endcase
end end
endmodule // pc mips_cpu_cpc cpc(
//Inputs for cpc
.clk(clk),
.rst(rst),
.cpc_in(out_npc_out),
//Outputs for cpc
.cpc_out(out_cpc_out),
.active(active)
);
mips_cpu_npc npc(
//Inputs for npc
.clk(clk),
.rst(rst),
.npc_in(in_npc_in),
//Outputs for npc
.npc_out(out_npc_out)
);
endmodule